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參數資料
| 型號： | W6694 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器) |
| 中文描述： | PCI總線的綜合業務數字網的S / T接口控制器（綜合業務數字網的PCI總線的S / T的接口控制器） |
| 文件頁數： | 42/98頁 |
| 文件大小： | 1338K |
| 代理商： | W6694 |
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Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-42 -
The microprocessor may either enforce a 1 (idle state) in MR, MX by setting the control bit MRC or MXC (MOCR register)
to 0, or enable the control of these bits internally by the W6692A according to the Monitor channel protocol. Thus, before a data
exchange can begin, the control bit MRC, or MXC should be set to 1 by the microprocessor.
The relevant status bits are:
For the reception of Monitor data: MDR (Monitor Channel Data Received )
MER (Monitor Channel End of Reception)
For the transmission of Monitor data: MDA (Monitor Channel Data Acknowledged )
MAB (Monitor Channel Data
Abort)
About the status bit MAC( Monitor Channel Transmit Active) indicates whether a transmission is progress
.
If set MAC = 0,
the previous transmission has been terminated. Before starting a transmission, the microprocessor should
verify that the transmitter is inactive.
If set MAC = 1, after having written data into the Monitor Transmit Channel (MOX) register, the microprocessor sets this
bit to 1. This enables the MX bit to go active (0), indicating the presence of valid Monitor data (contents of MOX) in the
corresponding frame.
The receiving device stores the Monitor byte in its MOR (Monitor Receive Register) and generates a MDR (Monitor Channel
Data Receive) interrupt status. Alerted by the MDR interrupt, the microprocessor reads the MOR register. When it is ready to
accept data, it sets the MR control bit MRC to 1 to enable the receiver to store succeeding Monitor channel bytes and
acknowledge them according to the Monitor channel protocol. In addition, it enables other Monitor channel interrupts by setting
Monitor Channel Interrupt Enable to 1.
The first Monitor channel byte is acknowledged by the receiving device setting the MR bit to 0. This causes a MDA (Monitor
Channel Data Acknowledge) interrupt status at the transmitter. A new Monitor channel data byte can now be written by the
microprocessor in MOX register. The MX bit is still in the active (0) state. The transmitter indicates a new byte in the Monitor
channel by returning the MX bit active after sending it once in the inactive state. The receiver stores the Monitor channel byte
in MOR register and generates a new MDR interrupt status. When the microprocessor has read the MOR register , the receiver
acknowledges the data by returning the MR bit active after sending it once in the inactive state. This in turn causes the
transmitter to generate a MDA interrupt status. This
″
MDA interrupt
write data
MDR interrupt
read data
MDA
interrupt
″
handshake procedure is repeated as long as the transmitter has data to send.
When the last byte has been acknowledged by the receiver (MDA interrupt status), the microprocessor sets the Monitor
channel Transmit Control bit MXC to 0. This enforces an inactive (1) state in the MX bit. Two frames of MX inactive signifies
the end of a message. Thus, a MER (Monitor channel End of Reception) interrupt status is generated by the receiver when the
MX is received in the inactive state in two consecutive frames. As a result, the microprocessor sets the MR control bit MRC to 0,
which in turn enforces an inactive state in the MR bit. This marks the end of the transmittion, making the MAC (Monitor
channel Active) bit return to 0.
During a transmission process, it is possible for the receiver to ask a transmission to be aborted by sending an inactive MR bit
value in two consecutive frames. This is effected by the microprocessor writing the MR control bit MRC to 0. An aborted
transmission is indicated by a MAB (Monitor Channel Data Abort) interrupt status at the transmitter.
7.9 PCI/MP Interface Circuit
7.9.1 PCI Slave Mode And Configuration Serial EEPROM
W6692A implements target mode function which meets PCI local bus specification revision 2.2 and PCI Power Management
1.1. All the signals are 5V, 33 MHz compatible. A single function, type 00h configuration header is implemented for control of
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