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參數資料
| 型號： | W6694 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器) |
| 中文描述： | PCI總線的綜合業務數字網的S / T接口控制器（綜合業務數字網的PCI總線的S / T的接口控制器） |
| 文件頁數： | 50/98頁 |
| 文件大小： | 1338K |
| 代理商： | W6694 |
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Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-50 -
RACT Receiver Active
Setting this bit activates the D_ch HDLC receiver. This bit can be read. The receiver must be in active state in order to receive
data.
XACTB Transmitter Active
Resetting this bit activates the D_ch HDLC transmitter. This bit can be read. The transmitter must be in active state in order
to transmit data. Note this bit is active LOW.
PMES PME Trigger Select
0 : PCI power management event triggered by D_RMR or D_RME interrupt
1 : PCI power management event triggered by layer 1enters F7 state
MFD Multiframe Disable
This bit is used to enable or disable the multiframe structure on S/T interface :
0 : Multiframe is enabled
1 : Multiframe is disabled
DLP Digital Loopback
Setting this bit activates the digital loopback function. The transmitted digital 2B+D channels are looped to the received
2B+D channels. Note that after hardware reset, the internal clocks will turn off if the S bus is not connected or if there is no
signal on the S bus. In this case, the C/I command ECK must be issued to enable loopback function.
RLP Remote Loopback
Setting this bit to "1" activates the remote loopback function. The received 2B channels from the S interface are looped to the
transmitted 2B channels of S interface. The D channel is not looped in this loopback function.
Bits 7, 4 Reserved
These bits are reserved. The write values are don't care, but are read as zero.
8.1.5 Timer 1 Register
Value after reset : 00H
7
T1MD
CNT6
T1MD Timer1 Mode
TIMR1
Read/Write Address 10H/04H
6
5
4
3
2
1
0
CNT5
CNT4
CNT3
CNT2
CNT1
CNT0
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