
Data Sheet
W6692A PCI ISDN S/T-Controller
RBC8
Publication Release Date:
Mar,2000
Revision 1.0
-77 -
LOV
RBC12 RBC11 RBC10
RBC9
LOV Message Length Overflow
Used in transparent mode only. A "1" in this bit indicates a received message
≥
8192 bytes. This bit is valid only after RME
interrupt and is cleared by the RACK command.
RBC12-8 Receive Byte Count
Used in transparent mode only. Five most significant bits of the total number of bytes are in a received frame. These bits are
valid only after a RME interrupt and remain valid until the frame is acknowledge via the RACK bit.
Note
: The frame length equals RBC12-0. This length is between 1 and 8191. After a RME interrupt, the number of data
available in B1_RFIFO is frame length modulus threshold.
Remainder = RBC12-0 MOD threshold
No of available data = remainder if remainder
≠
0 or
No of available data = threshold if remainder = 0
The remainder equals RBC5-0 if threshold is 64.
8.2.14 B1_ch Transmit Idle Pattern
Value after reset: FFH
7
6
IDLE7
IDLE6
IDLE5
IDLE7-0
This pattern is transmitted when the transmitter is active and transmit FIFO is empty. Valid in extended transparent mode
only.
B1_IDLE
Read/Write Address B4H/2DH
5
4
3
2
1
0
IDLE4
IDLE3
IDLE2
IDLE1
IDLE0
8.3 B2 HDLC controller
TABLE 8.5 REGISTER ADDRESS MAP: B2 CHANNEL HDLC
Offset
C0/30
C4/31
C8/32
CC/33
D0/34 R_clear B2_EXIR
Access Register Name
R
B2_RFIFO
W
B2_XFIFO
R/W
B2_CMDR
R/W
B2_MODE
Description
B2 channel receive FIFO
B2 channel transmit FIFO
B2 channel command register
B2 channel mode control
B2 channel extended interrupt