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參數資料
| 型號： | W6694 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器) |
| 中文描述： | PCI總線的綜合業務數字網的S / T接口控制器（綜合業務數字網的PCI總線的S / T的接口控制器） |
| 文件頁數： | 54/98頁 |
| 文件大小： | 1338K |
| 代理商： | W6694 |
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Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-54 -
This bit indicates the status of layer 1 D channel.
0: The layer 1 D channel is not ready. No transmission is allowed.
1: The layer 1 D channel is ready. Layer 2 can transmit data to layer 1.
Note : Due to design mistake, DRDY=1 does not mean S/T layer 1 is in F7 state. Software has to check “DRDY=1 and C/I
code=AI8/10” in order to transmit.
8.1.11 D_ch Receive Status Register
Value after reset: 20H
7
6
0
RDOV
CRCE
RDOV Receive Data Overflow
A "1" indicates that the D_RFIFO is overflow. The incoming data will overwrite data in the receive FIFO. The data overflow
condition will set both the status and interrupt bits. It is recommended that software must read the RDOV bit after reading data
from D_RFIFO at RMR or RME interrupt. The software must abort the data and issue a RRST command to reset the receiver if
RDOV = 1. The frame overflow condition will not set this bit.
CRCE CRC Error
This bit indicates the result of frame CRC check:
0: CRC correct
1: CRC error
RMB Receive Message Aborted
A "1" means that a sequence of seven 1's was received and the frame is aborted. Software must issue RRST command to reset
the receiver.
Note
: Normally D_RSTA register should be read by the microprocessor after a D_RME interrupt. The contents of D_RSTA are
valid only after a D_RME interrupt and remain valid until the frame is acknowledged via a RACK bit.
D_RSTA
Read
Address 28H/0AH
5
4
3
0
2
0
1
0
0
0
RMB
8.1.12 D_ch SAPI Address Mask
Value after reset: 00H
7
6
SAM7
SAM6
SAM5
This register masks(disables) the first byte address comparison of the incoming frame. If the mask bit is "1" the corresponding
bit comparisons with D_SAP1, D_SAP2 are disabled. Comparison with SAPG is always performed.
Note
: For the LAPD frame, the least significant two bits are the C/R bit and EA =0 bit. It is suggested that the comparison
with C/R bit be masked. EA=0 for two octet address frame e.g LAPD, EA=1 for one octet address frame.
D_SAM
Read/Write Address 2CH/0BH
5
4
3
2
1
0
SAM4
SAM3
SAM2
SAM1
SAM0
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