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參數資料
| 型號： | W6694 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器) |
| 中文描述： | PCI總線的綜合業務數字網的S / T接口控制器（綜合業務數字網的PCI總線的S / T的接口控制器） |
| 文件頁數： | 87/98頁 |
| 文件大小： | 1338K |
| 代理商： | W6694 |
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Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-87 -
Bits 14-13 Data_Scale Read
Used when interpreting the value of Data register. Not implemented. Read as 0.
Bits 12-9 Data_Select Read
Used to select which data is to be reported through the Data register and Data_Scale field. Not implemented. Read as 0.
Bit 8 PME_En Read/Write, Sticky
A "1" enables W6692A to assert PME#. When "0", PME# assertion is disabled. If the PME# is active, writing "0" to this bit
also clears the PME# signal.
Bits 7-2 Reserved
These bits are reserved and read as 0.
Bits 1-0 Power State Read/Write
Used to get or set the device's power state.
00b - D0: fully operational
01b - D1: Not responds to PCI IO and memory accesses (PCI transation may or may not present, bus clock and VCC
present), only responds to PCI configuration access, B2 HDLC stopped
10b - D2: Not responds to PCI IO and memory accesses (PCI transation may or may not present, bus clock may or may not
present, VCC present), only responds to PCI configuration access, B1 and B2 HDLCs stopped
11b - D3
hot
: only responds to PCI configuration access accesses (PCI transation may or may not present, bus clock may or
may not present, VCC may or may not present, 3.3Vaux present), a software re-initialization of the chip must be performed when
returns to D0
Note : When waken up by PME event, software must read ISTA register or issue RRST command to clear the queued interrupt
status bits.
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