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參數資料
| 型號： | W6694 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器) |
| 中文描述： | PCI總線的綜合業務數字網的S / T接口控制器（綜合業務數字網的PCI總線的S / T的接口控制器） |
| 文件頁數： | 86/98頁 |
| 文件大小： | 1338K |
| 代理商： | W6694 |
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Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-86 -
Bit 21 Device Specific Initialization
1 = Device specific initialization is needed. Default is 1.
Bit 20 Reserved
Reserved. Read as 0.
Bit 19 PME Clock
1 = PCI clock is needed for PME# assertion. Default is 0.
Bits 18-16 Version
Default is 010b to indicate PCI Power Management Revision 1.1 compliant.
Bits 15-8 Next Item Pointer
Hardwired to 00
H
, to indicate no further Capability list item.
Bits 7-0 Capability Identifier
Hardwired to 01
H
, to indicate a PCI Power Management Identifier.
8.4.11 Power Management Control/Status
PCI Configuration Address: 44
H
Default: 0000
H
for bits 31-16; X000,000X,0000,0000b for bits 15-0.
Read/Write
Address 44
H
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Operational Data
PMCSR_BSE
7
15
14
13
12
11
Power Management Control/Status Register (PMCSR)
10
9
8
6
5
4
3
2
1
0
Bits 31-24 Operational Data Report Read
Reports the power operational data of whole PCI card. Not implemented. Read as 0.
Bits 23-16 PMCSR PCI to PCI Bridge Support Extensions Read
Not implemented. Read as 0.
Bits 15-0 are the Power Management Control/Status register. A sticky bit has an indeterminate value at time of initial operating
system boot. (It is not set/preset by PCI reset signal.)
Bit 15 PME_Status Read/Write-clear, Sticky
This bit is set when W6692A would normally assert the PME# signal independent of the state of the PME_En bit
.
Writig a
"1" to this bit will clear it and cause W6692A to stop asserting a PME# (if enabled). Writing a "0" has no effect.
PME_En=0
PME-En=1
PME event
occurred
PME# inactive
PME# active until PME-
Status is cleared
No PME event
PME_Status=0
PME# inactive
PME# inactive
PME_Status=1
PME_Status=1
PME_Status=0
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