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參數資料
型號: W6694
廠商: WINBOND ELECTRONICS CORP
英文描述: PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器)
中文描述: PCI總線的綜合業務數字網的S / T接口控制器(綜合業務數字網的PCI總線的S / T的接口控制器)
文件頁數: 30/98頁
文件大小: 1338K
代理商: W6694
Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-30 -
Device
W6692A
Settings
k =2
Result
Pass
7.2.5.6 FAinfD_kfr
This is to test the number k of IX_I4noflag frames necessary for loss of frame alignment.
Device
Settings
W6692A
k = 2
Result
Pass
7.2.5.7 Faregain
This is to test the number m of good frames necessary for regain of frame alignment. The TE regains frame alignment at m+1
frame.
The W6692A achieves synchronization after 5 frames, i.e m=4.
Device
Settings
W6692A
m = 4
Result
Pass
7.2.6 Multiframe Synchronization
As specified by ITU-T I.430, the Q bit is transmitted from TE to NT in the position normally occupied by the auxiliary
framing bit (F
A
) in one frame out of 5, whereas the S bit is transmitted from NT to TE. The S and Q bit positions and multiframe
structure are shown in Table 7.6.
The functions provided by W6692A are:
- Multiframe synchronization: Synchronization is achived when the M bit pattern has been correctly received during
20 consecutive frames starting from frame number 1.
Note: Criterion for multiframe synchronization is not defined in I.430 Recommendation.
- S bits receive and detect: When synchronization is achieved, the four received S bits in frames 1,6,11,16 are stored
as S1 to S4 in the SQR register respectively. A change in the recived four bits (S1-4) is indicated by an interrupt.
- Multiframe synchronization monitoring: Multiframe synchronization is constantly monitored. The synchronization
state is indicated by the MSYN bit in the SQR register.
- Q bits transmit and F
A
mirroring: When multiframe synchronization is achived, the four bits Q1-4 stored in the
SQXR register are transmitted as the four Q bits (F
A
-bit position) in frames 1,6,11 and 16. Otherwise the F
A
bit
transmitted is a mirror of the received F
A
-bit. At loss of synchronization, the mirroring is resumed at the next F
A
-
bit.
- The multiframe synchronization can be disabled by setting MFD bit in the D_MODE register.
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