
Data Sheet
W6692A PCI ISDN S/T-Controller
3
2
1
0
0
OPS1
CODR3
CODR2 CODR1
CODX3
CODX2 CODX1
S1
S2
S3
Q1
Q2
Q3
OE1
OE0
XMODE PXC
MDR0
MER0
MDA0
MRIE0
MRC0
MXIE0
GRLP
SPU
PD
XA3
/IO3
/IO2
/IO1
XD3
XD2
/IO10
/IO9
EN
SK
CS
MDR1
MER1
MDA1
MRIE1
MRC1
MXIE1
IC1_3
IC1_2
IC1_1
IC1_3
IC1_2
IC1_1
IC2_3
IC2_2
IC2_1
IC2_3
IC2_2
IC2_1
CI1R_4
CI1R_3 CI1R_2
CI1X_4
CI1X_3 CI1X_2
MO0C
IC1
IC2
0
IC1
IC2
Publication Release Date:
Mar,2000
Revision 1.0
-48 -
Offset
R/W Name
54/15 R/W CTL
58/16 R
5C/17 R/W CIX
60/18 R
64/19 R/W SQX
68/1A R/W PCTL
6C/1B R
70/1C R/W MO0X
74/1D R_clr MO0I
78/1E R/W MO0C
7C/1F R/W GCR
F4/3D R/W XADDR
7
0
6
0
5
4
0
0
SRST
OPS0
CODR0
CODX0
S4
Q4
CIR
SCC
ICC
0
0
0
0
SQR
XIND1
XIND0
MSYN
SCIE
SCIE
OE2
0
0
0
OE5
OE4
OE3
MO0R
MAB0
MXC0
GMODE
XA0
/IO0
XD0
/IO8
SDO
MAB1
MXC1
IC1_0
IC1_0
IC2_0
IC2_0
CI1R_1
CI1X_1
CI1
CI1
0
0
0
0
MAC0
XA7
/IO7
XD7
MAC1
XA6
/IO6
XD6
GACT
XA5
/IO5
XD5
TLP
XA4
/IO4
XD4
XA2
XA1
F8/3E R/W XDATA
XD1
FC/3F R/W EPCTL
6D/40 R
71/41 R/W MO1X
75/42 R_clr MO1I
79/43 R/W MO1C
6E/44 R
72/45 R/W IC1X
6F/46 R
73/47 R/W IC2X
7D/48 R
7E/49 R/W CI1X
76/4A R_clr GCI_EXIR
7A/4B R/W GCI_EXIM
0
0
0
SDI
MO1R
0
0
0
0
IC1R
IC1_7
IC1_7
IC2_7
IC2_7
IC1_6
IC1_6
IC2_6
IC2_6
IC1_5
IC1_5
IC2_5
IC2_5
CI1R_6
CI1X_6
IC1_4
IC1_4
IC2_4
IC2_4
CI1R_5
CI1X_5
MO1C
MO1C
IC2R
CI1R
0
0
0
1
0
0
0
1
0
1
8.1.1 D_ch receive FIFO
The D_RFIFO has a length of 128 bytes.
After a D_RMR interrupt, exactly 64 bytes are available.
After a D_RME interrupt, the number of bytes available equals RBC5-0 bits in the D_RBCL register.
D_RFIFO
Read Address 00H/00H
8.1.2 D_ch transmit FIFO
The D_XFIFO has a length of 128 bytes.
D_XFIFO
Write Address 04H/01H