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參數(shù)資料
型號： W6694
廠商： WINBOND ELECTRONICS CORP
英文描述： PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器)
中文描述： PCI總線的綜合業(yè)務(wù)數(shù)字網(wǎng)的S / T接口控制器（綜合業(yè)務(wù)數(shù)字網(wǎng)的PCI總線的S / T的接口控制器）
文件頁數(shù)： 49/98頁
文件大?。?/td> 1338K
代理商： W6694
Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-49 -
After an D_XFR interrupt, up to 64 bytes of data can be written into this FIFO for transmission. At the first time, up to 128
bytes of data can be written.
8.1.3 D_ch command register
Value after reset: 00H
7
6
RACK
RRST
RACK Receive Acknowledge
After a D_RMR or D_RME interrupt, the processor must read out the data in D_RFIFO and then sets this bit to acknowledge
the interrupt. Writing “0” to this bit has no effect.
RRST Receiver Reset
Setting this bit resets the D_ch HDLC receiver and clears the D_RFIFO data. Writing “0” to this bit has no effect.
STT1 Start Timer 1
The timer 1 is started when this bit is set to one. The timer is stopped when it expires or by a write of the TIMR1 register.
Writing “0” to this bit has no effect.
XMS Transmit Message Start/Continue
Setting this bit will start or continue the transmission of a frame. The opening flag is automatically added by the HDLC
controller. Writing “0” to this bit has no effect.
XME Transmit Message End
Setting this bit indicates the end of frame transmission.. The D_ch HDLC controller automatically appends the CRC and the
closing flag after the data transmission. Writing “0” to this bit has no effect.
Note
: If the frame
≤
64 bytes, XME plus XMS commands must be issued at the same time.
XRST Transmitter Reset
Setting this bit resets the D_ch HDLC transmitter and clears the D_XFIFO. The transmitter will send inter frame time fill
pattern (which is 1's) immediately. This command also results in a transmit FIFO ready condition. Writing “0” to this bit has no
effect.
D_CMDR
Write
Address 08H/02H
5
0
4
3
2
0
1
0
STT1
XMS
XME
XRST
8.1.4 D_ch Mode Register D_MODE
Value after reset : 00H
7
6
0
RACT XACTB
Read/Write Address 0CH/03H
5
4
0
3
2
1
0
PMES
MFD
DLP
RLP
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