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參數資料
型號： W6694
廠商： WINBOND ELECTRONICS CORP
英文描述： PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器)
中文描述： PCI總線的綜合業務數字網的S / T接口控制器（綜合業務數字網的PCI總線的S / T的接口控制器）
文件頁數： 39/98頁
文件大小： 1338K
代理商： W6694
Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-39 -
In addition, flag recognition, CRC check and zero bit deletion are also performed. The result of CRC check is indicated in
Bn_STAR: CRCE bit. The data between opening flag and CRC field (not included) is stored in receive FIFO. Two interrupts are
used for the reception of data. The RMR interrupt in Bn_EXIR register indicates at least a threshold block of data have been put
in the receive FIFO. The RME interrupt in Bn_EXIR register indicates the end of frame has been received. The micro-processor
can read out a threshold length of data from receive FIFO at RMR interrupt, or all the data in receive FIFO at RME interrupt. At
each RMR/ RME interrupt, micro-processor must issue a Receive Message Acknowledgement(RACK) command to explicitly
acknowledge the interrupt.
The microprocessor reaction time for RMR/ RME interrupt depends on the FIFO threshold setting and B channel data rate.
For example, it is 8 ms if the FIFO threshold is 64 and the B channel data rate is 64 kbps.
If the microprocessor is late in handling the interrupt, the incoming additional bytes will result in a "data overflow" interrupt
and status bit.
Extended transparent mode
: In this mode, all data received are stored in the receive FIFO without any modification. Every
time up to a threshold length of data has been stored in the FIFO, a Bn_RMR interrupt is generated.
In this mode, there is no RME interrupt.
The microprocessor must react to the RMR interrupt in time, otherwise a "data overflow" interrupt and status bit will be
generated.
7.7.2 Transmission of Frames in B Channel
A 128-byte FIFO is provided in the transmit direction. The FIFO threshold can be set at 64 or 96 bytes. The transmitter and
receiver use the same FIFO threshold setting.
The transmit operations differ in both modes:
Transparent mode
:
In this mode, the following functions are performed by the transmitter automatically:
- Flag generation
- CRC generation
- Zero bit insertion
The fields such as address, control and information are provided by the microprocessor and are stored in transmit FIFO. To
start the frame transmission, the microprocessor issues a XMS (Transmit Message Start) command. The transmitter requests
another block of data via XFR interrupt when more than a threshold length of vacancies are left in the FIFO.The micro-processor
then writes up to a threshold length of data into the FIFO and activates the subsequent transmission of the frame by a XMS
command too. The microprocessor indicates the end of the frame transmission by issuing XME (Transmit Message End) and
XMS commands at the same time. The transmitter then transmits all the data left in the transmit FIFO and appends the CRC and
closing flag. After this, a XFR interrupt is generated.
The inter-frame time fill pattern can be programmed to 1's or flags.
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