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參數資料
| 型號： | W6694 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器) |
| 中文描述： | PCI總線的綜合業務數字網的S / T接口控制器（綜合業務數字網的PCI總線的S / T的接口控制器） |
| 文件頁數： | 72/98頁 |
| 文件大?。?/td> | 1338K |
| 代理商： | W6694 |
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Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-72 -
This bit is read/write. Read operation returns the previously written value.
XACTB Transmitter Active
"0": transmitter is active, 64 kHz clock is provided.
"1": transmitter is inactive, clock is LOW to save power.
This bit is read/write. Read operation returns the previously written value.
B1_128K 128K Mode
"1": Both B1 and B2 channels in layer 1 are combined into single layer 2 channel. The layer 2 B1 channel can operates in
transparent mode or extended transparent mode and layer 2 B2 channel is not used.
"0": Both B1 and B2 channels in layer 1 are not combined.
This bit is read/write. Read operation returns the previously written value.
XMS Transmit Message Start/Continue
In transparent mode, setting this bit initiates the transparent transmission of B1_XFIFO data. The opening flag is
automatically added to the message by the B1_ch HDLC controller. Zero bit insertion is performed on the data. This bit is also
used in subsequent transmission of the frame.
In extended transparent mode, settint this bit activates the transmission of B1_XFIFO data. No flag, CRC or zero bit insertion
is added on the data.
This bit is write-only. It's auto-clear.
XME Transmit Message End
In transparent mode, setting this bit indicates the end of the whole frame transmission. The B1_ch HDLC controller
transmits the data in FIFO and automatically appends the CRC and the closing flag sequence in transparent mode.
In extended transparent mode, setting this bit stops the B1_XFIFO data transmission.
This bit is write-only. It's auto-clear.
XRST Transmitter Reset
Setting this bit resets the B1_ch HDLC transmitter and clears the B1_XFIFO. The transmitter will send inter frame time fill
pattern on B channel in transparent mode, or idle pattern in extended transparent mode. This command also results in a transmit
FIFO ready condition.
This bit is write only. It's auto-clear.
8.2.4 B1_ch Mode Register B1_MODE
Value after reset: 00H
7
6
MMS
ITF
EPCM B1_SW1 B1_SW0 SW56
MMS Message Mode Setting
Determines the message transfer modes of the B1_ch HDLC controller:
Read/Write
Address 8CH/23H
5
4
3
2
1
0
FTS1
FTS0
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