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參數(shù)資料
型號: W6694
廠商: WINBOND ELECTRONICS CORP
英文描述: PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器)
中文描述: PCI總線的綜合業(yè)務(wù)數(shù)字網(wǎng)的S / T接口控制器(綜合業(yè)務(wù)數(shù)字網(wǎng)的PCI總線的S / T的接口控制器)
文件頁數(shù): 67/98頁
文件大小: 1338K
代理商: W6694
Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-67 -
MER1
Monitor channel 1 End of Reception
MDA1
Monitor channel 1 Data Acknowledged
The remote end has acknowledged the Monitor byte being transmitted.
MAB1
Monitor channel 1 Data Abort
8.1.39 Monitor Channel 1 Control Register
Value after reset: 00H
7
6
5
0
0
0
MRIE1 Monitor Channel 1 Receive Interrupt Enable
Monitor channel interrupt status MDR1, MER1 generation is enabled (1) or masked (0).
MRC1 MR Bit Control
Determines the value of the MR bit:
0: MR bit always 1. In addition, the MDR1 interrupt is blocked, except for the first byte of a packet (if MRE=1).
1: MR internally controlled by the W6692A according to Monitor channel protocol. In addition, the MDR1 interrupt is
enabled for all received bytes according to the Monitor channel protocol (if MRE=1).
MXIE1 Monitor channel 1 Transmit Interrupt Enable
Monitor interrupt status MDA1, MAB1 generation is enabled (1) or masked (0).
MXC1 MX bit Control
Determines the value of the MX bit:
0: MX always 1.
1: MX internally controlled by the W6692A according to Monitor channel protocol.
MO1C
Read/Write Address 79H/43H
4
0
3
2
1
0
MRIE1
MRC1
MXIE1
MXC1
8.1.40 GCI IC1 Receive Register
Value after reset: Undifined
7
6
Bit 7-0
Receive data of GCI IC1 channel.
IC1R
Read
Address 6EH/44H
5
4
3
2
1
0
8.1.41 GCI IC1 Transmit Register
Value after reset: FFH
7
6
IC1X
Read/Write
Address 72H/45H
5
4
3
2
1
0
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