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參數資料
| 型號： | W6694 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器) |
| 中文描述： | PCI總線的綜合業務數字網的S / T接口控制器（綜合業務數字網的PCI總線的S / T的接口控制器） |
| 文件頁數： | 73/98頁 |
| 文件大小： | 1338K |
| 代理商： | W6694 |
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Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-73 -
0: Transparent mode. In receive direction, address comparison is performed on each frame. The frames with matched
address are stored in B1_RFIFO. Flag deletion, CRC check and zero bit deletion are performed. In transmit direction, the data is
transmitted with flag insertion, zero bit insertion and CRC generation.
1: Extended transparent mode. In receive direction, all data are received and stored in the B1_RFIFO. In transmit
direction, all data in the B1_XFIFO are transmitted without alteration.
ITF Inter-frame Time Fill
Defines the inter-frame time fill pattern in transparent mode.
0 : Mark. The binary value "1" is transmitted.
1 : Flag. This is a sequence of "01111110".
EPCM Enable PCM Transmit/Receive
0 : Disable data transmit/ receive to/from PCM port. The frame synchronization clock PFCK1 is held LOW.
1 : Enable data transmit/ receive to/from PCM port. The frame synchronization clock PFCK1 is active.
B1_SW1-0 B Channel Switching Select
These two bits, along with PXC bit in PCTL register, determine the connection in B1 channel. See section 7.4 for details.
Note
: The connection with micro-controller is through HDLC controller. When HDLC connects with layer 1, either transparent
or extended transparent mode can be used. When HDLC connects with PCM port/GCI bus, only extended transparent mode can
be used and the EPCM bit must be set to enable PCM function.
SW56 Switch 56 Traffic
0: The data rate in B1 channel is 64 kbps.
1: The data rate in B1 channel is 56 kbps. The most significant bit in each octet is fixed at "1".
Note
: In 56 kbps mode, only transparent mode can be used.
FTS1-0 FIFO Threshold Select
These two bits determine the B1 channel receive and transmit FIFO's threshold setting. An interrupt is generated when the
number of received data or the number of vacancies in XFIFO reaches the threshold value.
FTS1
FTS0
Threshold (byte)
0
0
64
0
1
Reserved
1
0
96
1
1
Not allowed
8.2.5 B1_ch Extended Interrupt Register B1_EXIR
Value after reset: 00H
7
6
5
RMR
RME
RDOV
Read_clear
Address 90H/24H
4
3
2
1
0
XFR
XDUN
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