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參數(shù)資料
型號： W6694
廠商： WINBOND ELECTRONICS CORP
英文描述： PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器)
中文描述： PCI總線的綜合業(yè)務(wù)數(shù)字網(wǎng)的S / T接口控制器（綜合業(yè)務(wù)數(shù)字網(wǎng)的PCI總線的S / T的接口控制器）
文件頁數(shù)： 4/98頁
文件大小： 1338K
代理商： W6694
Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-4 -
8.1 C
HIP
C
ONTROL AND
D_
CH
HDLC
CONTROLLER
................................................................................................................. 46
8.1.1 D_ch receive FIFO
D_RFIFO Read Address 00H/00H........................................................................................ 48
8.1.2 D_ch transmit FIFO
D_XFIFO Write Address 04H/01H...................................................................................... 48
8.1.3 D_ch command register
D_CMDR Write Address 08H/02H............................................................................... 49
8.1.4 D_ch Mode Register
D_MODE Read/Write Address 0CH/03H............................................................................... 49
8.1.5 Timer 1 Register
TIMR1 Read/Write Address 10H/04H...................................................................................... 50
8.1.6 Interrupt Status Register
ISTA Read_clear Address 14H/05H...................................................................... 51
8.1.7 Interrupt Mask Register
IMASK Read/Write Address 18H/06H............................................................................... 52
8.1.8 D_ch Extended Interrupt Register
D_EXIR Read_clear Address 1CH/07H............................................................. 52
8.1.9 D_ch Extended Interrupt Mask Register
D_EXIM Read/Write Address 20H/08H.................................................... 53
8.1.10 D_ch Status Register
D_XSTA Read Address 24H/09H.................................................................................. 53
8.1.11 D_ch Receive Status Register
D_RSTA Read Address 28H/0AH ....................................................................... 54
8.1.12 D_ch SAPI Address Mask
D_SAM Read/Write Address 2CH/0BH..................................................................... 54
8.1.13 D_ch SAPI1 Register
D_SAP1 Read/Write Address 30H/0CH............................................................................ 55
8.1.14 D_ch SAPI2 Register
D_SAP2 Read/Write Address 34H/0DH .............................................................................. 55
8.1.15 D_ch TEI Address Mask
D_TAM Read/Write Address 38H/0EH.......................................................................... 55
8.1.16 D_ch TEI1 Register
D_TEI1 Read/Write Address 3CH/0FH............................................................................. 55
8.1.17 D_ch TEI2 Register
D_TEI2 Read/Write Address 40H/10H.............................................................................. 56
8.1.18 D_ch Receive Frame Byte Count High
D_RBCH Read Address 44H/11H......................................................... 56
8.1.19 D_ch Receive Frame Byte Count Low
D_RBCL Read Address 48H/12H........................................................... 56
8.1.20 Timer 2
TIMR2 Write Address 4CH/13H.......................................................................... 57
8.1.21 Layer 1_Ready Code
L1_RC Read/Write Address 50H/14H................................................. 57
8.1.22 Control Register
CTL Read/Write Address 54H/15H............................................................................................. 57
8.1.23 Command/Indication Receive Register
CIR Read Address 58H/16H................................................................. 58
8.1.24 Command/Indication Transmit Register
CIX Read/Write Address 5CH/17H..................................................... 59
8.1.25 S/Q Channel Receive Register
SQR Read Address 60H/18H......................................................................... 59
8.1.26 S/Q Channel Transmit Register
SQX Read/Write Address 64H/19H.............................................................. 60
8.1.27 Peripheral Control Register
PCTL Read/Write Address 68H/1AH ............................................................. 60
8.1.28 Monitor Receive Channel 0
MO0R Read Address 6CH/1BH...................................................................... 61
8.1.29 Monitor Transmit Channel 0
MO0X Read/Write Address 70H/1CH........................................................... 61
8.1.30 Monitor Channel 0 Interrupt Register
MO0I Read_clear Address 74H/1DH.............................................. 62
8.1.31 Monitor Channel 0 Control Register
MO0C Read/Write Address 78H/1EH...................................................... 62
8.1.32 GCI Mode Control/Status Register
GCR Read/Write Address 7CH/1FH.................................. 62
8.1.33 Peripheral Address Register
XADDR Read/Write Address F4H/3DH......................................................... 64
8.1.34 Peripheral Data Register
XDATA Read/Write Address F8H/3EH.............................................................. 65
8.1.35 Serial EEPROM Control Register
EPCTL Read/Write Address FCH/3FH.......................................................... 65
8.1.36 Monitor Receive Channel 1 Register
MO1R Read Address 6DH/40H............................................................. 66
8.1.37 Monitor Transmit Channel 1 Register
MO1X Read/Write Address 71H/41H .................................................. 66
8.1.38 Monitor Channel 1 Interrupt Register
MO1I Read_clear Address 75H/42H............................................... 66
8.1.39 Monitor Channel 1 Control Register
MO1C Read/Write Address 79H/43H....................................................... 67
8.1.40 GCI IC1 Receive Register
IC1R Read Address 6EH/44H ........................................................................ 67
8.1.41 GCI IC1 Transmit Register
IC1X Read/Write Address 72H/45H.............................................................. 67
8.1.42 GCI IC2 Receive Register
IC2R Read Address 6FH/46H......................................................................... 68
8.1.43 GCI IC2 Transmit Register
IC2X Read/Write Address 73H/47H.............................................................. 68
8.1.44 GCI CI1 Indication Register
CI1R Read Address 7DH/48H.................................................................... 68
8.1.45 GCI CI1 Command Register
CI1X Read/Write Address 7EH/49H........................................................... 68
8.1.46 GCI Extended Interrupt Register
GCI_EXIR Read_clear Address 76H/4AH ......................................................... 69
8.1.47 GCI Extended Interrupt Mask Register
GCI_EXIM Read/Write Address 7AH/4BH............................................... 69
8.2 B1 HDLC
CONTROLER
...................................................................................................................................................... 69
8.2.1 B1_ch receive FIFO
B1_RFIFO Read Address 80H/20H............................................................................... 71
8.2.2 B1_ch transmit FIFO
B1_XFIFO Write Address 84H/21H .......................................................................... 71
8.2.3 B1_ch command register
B1_CMDR Read/Write Address 88H/22H............................................................... 71
8.2.4 B1_ch Mode Register
B1_MODE Read/Write Address 8CH/23H........................................................................ 72
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