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參數資料
| 型號： | W6694 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器) |
| 中文描述： | PCI總線的綜合業務數字網的S / T接口控制器（綜合業務數字網的PCI總線的S / T的接口控制器） |
| 文件頁數： | 58/98頁 |
| 文件大小： | 1338K |
| 代理商： | W6694 |
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Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-58 -
SRST Software Reset
When this bit is set to "1", a software reset signal is activated. The effects of this reset signal are equivalent to the hardware
reset pin , except that it does not reset the PCI interface circuit.
This bit is not auto-clear, the software must write "0" to this bit to exit from the reset mode.
Note
: When SRST = 1, the chip is in reset state. Read or write to any of the registers is inhibited at this time. The SRST bit is
write-only.
OPS1-0 Output Phase Delay Compensation Select1-0
These two bits select the output phase delay compensation.
OPS1
OPS0 Effect
0
0
No output phase delay compensation
0
1
Output phase delay compensation 260ns
1
0
Output phase delay compensation 520 ns
1
1
Output phase delay compensation 1040 ns
8.1.23 Command/Indication Receive Register
Value after reset: 0FH
7
6
5
SCC
ICC
SCC S Channel Change
A change in the received 4-bit S channel has been detected. The new code can be read from the SQR register. This bit is
cleared via a read of the SQR register.
ICC Indication Code Change
A change in the received indication code has been detected. The new code can be read from the CIR register. This bit is
cleared by a read of the CIR register.
CODR3-0 Layer 1 Indication Code
Value of the received layer 1 indication code. Note these bits have a buffer size of two.
Note
: If S/T layer 1 function is disabled and GCI slave mode is enabled (GMODE = 1 in GCR register), CIR register is used to
receive layer 1 indication code from U transceiver. In this case, SCC bit is not used and the supported indication codes are :
Indication
Symbol
Code
Descriptions
Deactivation confirmation
DC
1111
Idle code on GCI interface
Power up indication
PU
0111
U transceiver power up
CIR
Read
Address 58H/16H
4
3
2
1
0
CODR3 CODR2 CODR1 CODR0
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