
Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-64 -
- To reset the SPU bit and wait for the following ICC (indication code change) interrupt.
Unused.
1
1
GMODE GCI Mode
.
0: Layer 1 is S/T interface; GCI is in master mode. This is default setting.
1: Layer 1 is U interface; GCI is in slave mode.
8.1.33 Peripheral Address Register
Value after reset: Undefined
The register content depends on PCTL:XMODE setting.
XMODE = 0 : Simple IO mode, Valid in PCI or Intel/Motorola Bus mode
7
6
5
4
IO7
IO6
IO5
IO4
IO1-0 Read or Write Data of Pins IO1-0
On read operation, these are the present values of pins IO1-0.
On write operation, the data are driven to pins IO1-0 only if PCTL:OE0=1.
IO3-2 Read or Write Data of Pins IO3-2
On read operation, these are the present values of pins IO3-2.
On write operation, the data are driven to pins IO3-2 only if PCTL:OE1=1.
IO5-4 Read or Write Data of Pins IO5-4
On read operation, these are the present values of pins IO5-4.
On write operation, the data are driven to pins IO5-4 only if PCTL:OE2=1.
IO7-6 Read or Write Data of Pins IO7-6
On read operation, these are the present values of pins IO7-6.
On write operation, the data are driven to pins IO7-6 only if PCTL:OE3=1.
XMODE = 1: 8-bit multiplexed microprocessor mode, Valid in PCI Bus mode only
7
6
5
4
XA7
XA6
XA5
XA4
XA7-0 Peripheral Address
XADDR
Read/Write
Address F4H/3DH
3
2
1
0
IO3
IO2
IO1
IO0
3
2
1
0
XA3
XA2
XA1
XA0