
Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-85 -
Bits 7-0 Interrupt Line R/W
This 8-bit register is used to communicate interrupt line routing information. BIOS or OS software must write the routing
information into this register as it initializes and configures the system.
8.4.9 Capability Pointer
PCI Configuration Address: 34
H
Default: 40
H
Read
Address 34
H
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Not Implemented
Not Implemented
7
15
14
13
12
11
10
9
8
6
5
4
3
2
1
0
Not Implemented
Capability Pointer
Bit 7-0 Capability Pointer
Hardwired to 40
H
to indicate the Power Management Capability list begins at offset 40
H
.
8.4.10 Power Management Capability
PCI Configuration Address: 40
H
Default: FE62 00 01
H
Read
Address 40
H
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Power Management Capability
7
15
14
13
12
11
10
9
8
6
5
4
3
2
1
0
Next Item Pointer
Capability Identifier
Bits 31-16 are Power Management Capability register. It is loaded from EEPROM at power on if EEPROM is not empty, else the
default value is used.
Bit 31-27 PME-Support
Indicate states which can assert PME# signal:
XXXX1b - PME# can be asserted from D0
XXX1Xb - PME# can be asserted from D1
XX1XXb - PME# can be asserted from D2
X1XXXb - PME# can be asserted from D3
hot
1XXXXb - PME# can be asserted from D3
cold
Default is 11111b.
Bit 26 D2_Support
1 = D2 state is supported. Default is 1.
Bit 25 D1_Support
1 = D1 state is supported. Default is 1.
Bits 24-22 Aux_Current
Indicating current requirement of 3.3Vaux at D3
cold
. Default is 001b (55 mA).