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參數資料
| 型號： | W6694 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器) |
| 中文描述： | PCI總線的綜合業務數字網的S / T接口控制器（綜合業務數字網的PCI總線的S / T的接口控制器） |
| 文件頁數： | 38/98頁 |
| 文件大小： | 1338K |
| 代理商： | W6694 |
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Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-38 -
The inter-frame time fill pattern must be all 1's, according to ITU-T I.430.
Collisions which occur on the D channel of S interface will cause an D_EXIR:XCOL interrupt. A XRST (Transmitter Reset)
command must be issued and software must wait until transmit FIFO ready (via XFR interrupt), re-write data, and issue XMS
command to re-transmit the data.
7.7 B Channel HDLC Controller
There are two B channel HDLC controllers. Each B channel HDLC controller provides two operation modes :
- Transparent mode
Characteristics :
* 2 byte address field
* Receive address comparison maskable bit-by-bit
* Data between opening flag and CRC (not included) stored in receive FIFO
* Flag generation/ deletion
* Frame Check Sequence generation/ check with CRC_ITU-T polynominal
* Zero bit insertion/ deletion
- Extended transparent mode
Characteristics :
* All data transmitted/ received without modification
* No address comparison
* No flag generation/ detection
* No FCS generation/ check
* No bit stuffing
For PCM-HDLC connection, only extended transparent mode can be selected.
The data rate in B channel can be set at 64 kbps or 56 kbps by the B1_MODE (B2_MODE) : SW56 bit.
7.7.1 Reception of Frames in B Channel
A 128-byte FIFO is provided in the receive direction. The receive FIFO threshold can be set at 64 or 96 bytes by the
Bn_MODE register. If the number of received data reaches the threshold, a Receive Message Ready (RMR) interrupt will be
generated.
The operations for reception of frames differ in each mode:
Transparent mode
: The received frame address is compared with the contents in receive address registers. In addition, the
comparisons can be selectively masked bit-by-bit via address mask registers. Comparison is disabled when the corresponding
mask bit is "1".
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