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參數(shù)資料
型號(hào): W88227QD
廠商: WINBOND ELECTRONICS CORP
元件分類: 消費(fèi)家電
英文描述: ATAPI CD-ROM Decoder(支持ATAPI標(biāo)準(zhǔn)的CD-ROM解碼器)
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP128
封裝: LQFP-128
文件頁數(shù): 14/116頁
文件大小: 787K
代理商: W88227QD
Preliminary/Confidential
Subject to change without notice
W88227F/W88227QD
- 10 -
1999/10/1 Rev: 0.70
2.1.3 Clock Source and Power Management
If the frequency on UXI is 33.8688 MHz, then the crystal on DXI can be saved. If the frequency on UXI is not
33.8688 MHz, then the input frequency on DXI must be 33.8688 MHz to support audio playback. A clock
output pin CKO can be used as clock source. If
CKOSTP (43h.2)
is set high, the output of pin CKO holds a
"high" status so that the external device is in idle mode. Note that DXI should be connected to ground if not
used.
1
0
playback
logic
uP
module
programmable
system clock
ECC logic
& DRAM I/F
UDMA logic
ACLK=33.8688MHz
DXI
DXO
UXI
UXO
DCLKS (43h.0)
1
0
UCLKS(8Ah.3)
1
0
APINS (90h.4)
PSKCTL (59h)
PSKEN (1Ah.w4)
1
0
ACLKS (43h.1)
DCLK
SCLK
CKO
+
CKOSTP (43h.2)
Decoder Idle Mode
Setting
CKSTP (19h.w7)
stop the clock of decoder. The decoder exits idle mode on reset or host command.
UP8032 Idle Mode
Setting the
IDL (PCON.0)
high stop the clock of uP8032. The peripherals and the interrupt logic continue to be
clocked. The processor will exit idle mode when either an interrupt or a reset occurs.
Power-Down Mode
When
PD (PCON.1)
is set high, the chip enters the power-down mode. In this mode, the crystal feedback loop
between UXI and UXO can be closed by setting
PD (PCON.1)
high, and that between DXI and DXO can be
closed by setting
XOFF (8Ah.7)
high. In two-crystal case,
XOFF
should be set before
PD
. These two loops
resume on the following conditions.
EA
EHWK
EIWK
HIIEN
ARSTIEN
wake-up event
x
x
x
x
x
power on reset or host reset
1
1
x
1
x
software reset by setting SRST high
1
1
x
x
1
DEVICE RESET command
1
x
1
x
x
interrupt on INT0 or INT1
Before entering power-down mode, internal pull-up resistors can be closed by setting
PUCTL (98h).
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