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參數資料
| 型號： | W88227QD |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 消費家電 |
| 英文描述： | ATAPI CD-ROM Decoder(支持ATAPI標準的CD-ROM解碼器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | LQFP-128 |
| 文件頁數： | 29/116頁 |
| 文件大小： | 787K |
| 代理商： | W88227QD |
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Preliminary/Confidential
Subject to change without notice
W88227F/W88227QD
- 25 -
1999/10/1 Rev: 0.70
2.2.4 Decoder Logic
2.2.4.1 Sync Detection/Insertion
The sync field of CD-ROM data is recorded as following: 1 (00h) bytes, 10 (FFh) bytes and 1 (00h) byte. This
sync field is detected for sector synchronization if
SDEN (0Bh.w6)
is enabled. To prevent loss of
synchronization caused by broken sync, an internal counter can provide inserted sync signal if
SIEN (0Bh.7)
is
enabled. There are no sync bytes in CD-DA format, so
SDEN (0Bh.w6)
should not be set.
2.2.4.2 Descramble
Bytes 12 to 2351 of each CD-ROM sector is scrambled in decoding. Setting
DSCREN (0Bh.5)
high enables the
descramble logic. Descramble logic should be disabled while reading of CD-DA data.
2.2.4.3 Disk-Monitor Mode
The decoder logic is in disk-monitor mode if
CTRL0 (0Ah,w)
is set as 80h. In disc-monitor mode, no ECC
correction and EDC checking is carried. The sector ready interrupt flag
SRIb (01h.r5)
is immediately
generated when the header bytes are available in
HEAD0-3 (04h-07h,r)
. The header bytes in disc-monitor
mode are less trustworthy than that in buffer-correction mode.
2.2.4.4 Parallel ECC Correction
The error correction of the CD-ROM sector is carried by a Reed-Solomon Product-Like Code (RSPC). The
RSPC is a product code over GF(2
8
) field which is generated by the primitive polynomial
P(x) = x
8
+ x
4
+ x
3
+ x
2
+ 1
The primitive element
α
of GF(2
8
) is
α
= (00000010)
where the right-most bit is the least significant bit.
The data is divided into high byte plane and low byte plane before decoding. The RSPC decoding, operating on
bytes, is then applied twice, once to the high byte plane, once to the low byte plane.
To improve the efficiency of RSPC decoding, a parallel ECC correction logic is implemented on chip. After
sync detection and descramble, the parallel ECC correction is carried on high byte plane and low byte plane
simultaneously. This correction scheme is about 33% faster than conventional decoder.
The Q-code correction and P-code correction are enabled by
QCEN (0Ah.w1)
and
PCEN (0Ah.w0)
respectively.
If both correction operations are enabled, Q-code correction is executed first. The corrected data are written
back to external RAM if
CWEN (0Bh.w4)
is high.
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