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參數(shù)資料
| 型號： | W88227QD |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 消費家電 |
| 英文描述： | ATAPI CD-ROM Decoder(支持ATAPI標準的CD-ROM解碼器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | LQFP-128 |
| 文件頁數(shù)： | 84/116頁 |
| 文件大小： | 787K |
| 代理商： | W88227QD |
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Preliminary/Confidential
Subject to change without notice
W88227F/W88227QD
- 80 -
1999/10/1 Rev: 0.70
Bit 5: QEN - Q-channel extraction enable
Setting this bit high enables Q-channel extraction logic. This pin should be set high only when
SCEN
(2Ch.w6)
is high. Once decoder and Q-channel extraction are both enabled, the extracted Q-channel
bytes are written into the DRAM starting from offset 9E0h of each block regardless of what mode of
data is set.
Bit 4: QMSF - Q-channel MSF auto-load enable
If Q-channel extraction logic is enabled, setting this bit high enables the MSF bytes of Q-channel to be
automatically loaded to
HEAD0-2 (04h-06h,r)
. The register
HEAD3 (07h,r)
hold first byte of
DATA-
Q,
(CONTROL and ADR) or 0xFFh if CRC checking of Q-channel is erroneous
.
Bit 3: ASTOPB - Automatic Decoder Stop on Error
If this bit is low, decoder would automatically stop on the following conditions:
HCEI (80h.r0)
activates if
HCEEN (80h.w0)
is enabled.
TNFI (80h.r1)
activates if
TNFEN (80h.w1)
is enabled.
LTTI (80h.r2)
activates if
LTTEN (80h.w2)
is enabled.
LASTBK (80h.r3)
activates if
BLIMEN (9Ah.5)
is enabled
DSFULI (80h.r4)
activates if
DSCEN (80h.w6)
is enabled.
STAERR (80h.r6)
activates if any Status Mask Bit is enabled
If this bit is low, the consistency of f/w and h/w should be carefully maintained. If this bit is high, the
decoder is controlled by microprocessor. This bit is default low after chip reset.
Bit 2: LTTEN - Larger Than Target Interrupt Enable
Setting this bit high enables
LTTI (80h.r2)
to be reflected on
SRIb (01h.r5)
.
Bit 1: TNFEN - Target Not Found Interrupt Enable
Setting this bit high enables
TNFI (80h.r1)
to be reflected on
SRIb (01h.r5)
.
Bit 0: HCEEN - Header Compare Error Interrupt Enable
Setting this bit high enables
HCEI (80h.r0)
to be reflected on
SRIb (01h.r5)
.
TARSTA - Target Status Register - (read 80h)
This register is 0 after chip reset, host reset, firmware reset and decoder reset. Reading this register
deactivates
SRIb (01h.r5)
.
Bit 7:
TARGED - Target Is Found
This bit is high after the target is found.
Bit 6:
STAERR - Status Error Flag
This bit becomes high if any status bit error, enabled by its corresponding mask bit, occurs at the end
of EDC-checking. This flag is deactivated after reading register
TARSTA (80h,r)
.
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