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參數(shù)資料
| 型號(hào)： | W88227QD |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | ATAPI CD-ROM Decoder(支持ATAPI標(biāo)準(zhǔn)的CD-ROM解碼器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | LQFP-128 |
| 文件頁(yè)數(shù)： | 60/116頁(yè) |
| 文件大小： | 787K |
| 代理商： | W88227QD |
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Preliminary/Confidential
Subject to change without notice
W88227F/W88227QD
- 56 -
1999/10/1 Rev: 0.70
CCTL1 - Clock Control Register 1 - (write 1Ah)
This register is 0 after chip reset.
Bit 7,6: obsolete
Bit 5:
XININV - Inverted XIN as System Clock
When this bit is high, the internal system clock is inverted from crystal input
.
PSKEN - Programmable System Clock Enable
Bit 4:
When this bit is high, the frequency of internal system clock is controlled by register
PSKCTL (59h).
Bit 3,2: CLK[1:0] - obsolete
Bit 1:
Reserved
Bit 0:
XTALD2 - Crystal Divided by 2
The internal clock frequency is half of crystal frequency if this bit is high.
VER - Version Register - (read 1Ah)
This register is used to hold the version number.
DSPSL - DSP Selection Register - (write 1Bh)
Bit 7:
C2ML - C2 MSB to LSB
When this bit is high, the sequence of erasures via
pin C2PO/SDATA2
is from MSB to LSB.
S16O - Select 16 Offset
Bit 6:
The incoming serial data is latched one clock after
pin LRCK
changes if this bit is high.
LCHP - Left Channel Polarity
Bit 5:
The incoming serial data is latched as left channel when
pin LRCK
is high if this bit is high.
SFT8 - Shift 8 Clocks
Bit 4:
The incoming serial data is latched by delay 8 clocks if this bit is high.
Bit 3: D2EN - SDATA2 Enable
Setting this bit high configures
pin C2PO/SDATA2
as second serial data input.
Bit 2:
SEL16 - Select 16 Bits Per Channel
The incoming serial data is latched 16 times per channel if this bit is high.
Bit 1:
DIR - Data Direction
Setting this bit high selects the direction of data from
pin SDATA
from MSB to LSB.
EDGE - Latching Edge Select
Bit 0:
Setting this bit high selects the rising edge of BCK for latching data from
pin SDATA
.
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