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參數資料
| 型號： | W88227QD |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 消費家電 |
| 英文描述： | ATAPI CD-ROM Decoder(支持ATAPI標準的CD-ROM解碼器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | LQFP-128 |
| 文件頁數： | 24/116頁 |
| 文件大小： | 787K |
| 代理商： | W88227QD |
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Preliminary/Confidential
Subject to change without notice
W88227F/W88227QD
- 20 -
1999/10/1 Rev: 0.70
2.2.1.4 Linear Address v.s. Block-Offset Address
The microprocessor can write/read external RAM through register
RAWR/RAMRD (1Eh)
based on linear
address defined by
RACU/H/L (2Dh/1Dh/1Ch,w)
. But the operation of data transfer from DRAM to host can
base on block-offset address or linear address. The following equation defines the relation between these two
types of address.
linear address = (block number
×
block size) + address offset
<Example 1> Data Transfer in Working Area
Conditions: 64 bytes of TOC data are stored starting from linear address 3EA00h at disc initialization and
TOC is requested by host (block size is A00h).
A) Sequence at disc initialization:
a) set RACL (1Ch) as 00h
b) set RACH (1Dh) as EAh
c) set RACU (2Dh) as 03h
d) wait UTBY (1Fh.7) low
e) write data to register RAMWR (1Eh)
f) goto step e) until all 64 bytes are written to DRAM
B1) Setting for
block-offset address
transfer:
- set TBH/L (25h/24h) as 0064h
- set TACH/L (05h/04h) as 0200h
- set TWCH/L (03h/02h) as 001Fh
B2) Setting for
linear address
transfer:
- set RACL (1Ch) as 00h
- set RACH (1Dh) as EAh
- set RACU (2Dh) as 03h
- set TWCH/L (03h/02h) as 801Fh
<Example 2> Data Transfer in User Area
Case 1: The 2048 bytes of user data are requested by host.
set TBH/L (25h/24h) as 001Fh
set TWCH/L (03h/02h) as 03FFh
set TACH/L (05h/04h) as 0010h
Case 2: The 288 bytes of EDC&ECC data are request by host.
set TBH/L (25h/24h) as 001Fh
set TWCH/L (03h/02h) as 008Fh
set TACH/L (05h/04h) as 0810h
If the requested data is not stored continuously in DRAM, e.g., header and EDC&ECC data, more than one
transfer has to be triggered.
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