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參數資料
| 型號： | W88227QD |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 消費家電 |
| 英文描述： | ATAPI CD-ROM Decoder(支持ATAPI標準的CD-ROM解碼器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | LQFP-128 |
| 文件頁數： | 43/116頁 |
| 文件大小： | 787K |
| 代理商： | W88227QD |
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Preliminary/Confidential
Subject to change without notice
W88227F/W88227QD
- 39 -
1999/10/1 Rev: 0.70
Bit 4:
HCIb - Host Command Interrupt Flag
This bit is activated by the following events:
(1) Host set bit SRST in ATAPI Device Control Register, if
HIIEN(2Eh.7)
is enabled. This event
also activates flag SRST (2Fh.r7). The interrupt is acknowledged by master reset, reading
ATCMD (37h)
or setting
CLRBSY (20h.4)
high.
(2) Host issues command other than PACKET and DEVICE RESET command to this drive, if drive
is selected and
HIIEN(2Eh.7)
is enabled. This event also activates flag
ATAC (2Fh.6)
. This flag
and interrupt is acknowledged by master reset, reading
ATCMD (37h)
or setting
CLRBSY (20h.4)
high.
(3) Host issues Execute Drive Diagnostics Command, if
HIIEN(2Eh.7)
is enabled. This event also
activates flag
DIAG (2Fh.r6).
This flag and interrupt is acknowledged by master reset, reading
ATCMD (37h)
or setting
CLRBSY (20h.4)
high.
(4) Host issues command to a non-exist slave drive, if
SHIEN(2Eh.2)
is enabled. This event also
activates flag
SHDC (2Fh.r4).
This flag and interrupt is acknowledged by master reset, reading
ATCMD (37h)
or setting
CLRBSY (20h.4)
high.
(5) Host issues DEVICE RESET Command, if
ARSTIEN(2Fh.1)
is enabled. This event also activates
flag
ARST (2Fh.r3).
This flag and interrup is acknowledged by writing any value to
ARSTACK
(30h,w).
TBSYb - Transfer Busy Flag
Bit 3:
This bit becomes active-low when the data transfer to host is triggered by the following events:
Writing any value to register
THTRG (06h,w)
Setting bit
ADTT (17h.w2)
high
After host read the last byte to be transferred, this flag is deactivated.
Bit 2:
APIb - Audio Playback Interrupt Flag
If
APOUT (90h,1-0)
are not zero, this bit is used as audio-playback-interrupt flag. If
APIEN (90h.6)
is
high, this bit activats whenever the playback of one block is finished, The corresponding interrupt is
acknowledged by writing any value to
APACK (97h,w).
DFRDYb - Data FIFO Ready
Bit 1:
After data transfer is triggered, the 32-byte Data FIFOs is automatically filled. This bit is used to
indicate that the Data FIFOs is ready to be read by the host for debugging. The Data FIFO is
automatically cleared in any of the following conditions:
Chip reset, host reset and firmware reset
DTEN (01h.w1)
is 0
DINB (1Fh.w1)
is 1
DFRST (2Bh.w3)
is 1
The end of data-in transfer
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