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參數資料
| 型號： | W88227QD |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 消費家電 |
| 英文描述： | ATAPI CD-ROM Decoder(支持ATAPI標準的CD-ROM解碼器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | LQFP-128 |
| 文件頁數： | 59/116頁 |
| 文件大?。?/td> | 787K |
| 代理商： | W88227QD |
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Preliminary/Confidential
Subject to change without notice
W88227F/W88227QD
- 55 -
1999/10/1 Rev: 0.70
Bit 3:
STWCEN - Set Transfer Word Count Enable
When this bit is high, the value
(TWCH/L + 1)
×
2
is loaded into ATBLO and ATBHI when
ADTT (17h.2) is triggered and PIO (1Fh.2) has been set high. If
ACMEN (9Ch.6)
is not enabled,
control bit
STWCEN
should not be set for Multiple Block Transfer. Instead, ATBHI/LO should be set
by firmware to
: (MBC4-0 + 1)
×
(TWCH/L + 1)
×
2.
AUCRCEN - Automatic Ultra DMA CRC Error Logic Enable
Bit 2:
If
AUCRCEN (18h.2)
is set high, the automatic status complete logic would be stopped if
UCRCOKB
(30h.r3)
is high. If no CRC error has occurred in last Ultra DMA burst, status complete sequence
would be automatically executed. This bit should be set high only if
ASCEN (18h.5)
is set high as
well. This bit is automatically clear when: (1) automatic status complete sequence is triggered or (2)
SCT (17h.w0)
is set high.
ABYEN - Automatic BSY Set Enable
Bit 1:
When this bit is high, the following sequence is executed when Disk Seek Complete is triggered by
DSCT (17h.w5)
:
Set BSY
DSC (37h.4)
←
1
Clear BSY
DSCT
←
0
A0IEN - A0h Command Interrupt Enable
Bit 0:
If this bit is high and
APKTEN (18h.7)
has been enabled,
HIRQ (2Eh.3)
becomes active-high after an
opcode A0h is issued to ATA Command Register.
CCTL0 - Clock Control Register 0 - (write 19h)
This register is 0 after chip reset.
Bit 7:
CKSTP - Clock Stop
Setting his bit high stops the internal clock. CKSTP is de-activated by the following events:
Master reset or firmware reset
Command write from the host while the drive is selected
Host issues Diagnostic Command, regardless of drive selection
Host issues command to shadow drive if SHDRV (3Fh.6) is enabled
Host set bit SRST in ATAPI Device Control Register high, regardless of drive selection
Bit 6-4: reserved
Bit 3-0: CKS[3:0] - Clock Skew Control
CKS3-0 are used to control the duty cycle of the internal clock. The low period of cycle increases as
the skew value increments.
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