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參數(shù)資料
| 型號(hào)： | W88227QD |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | ATAPI CD-ROM Decoder(支持ATAPI標(biāo)準(zhǔn)的CD-ROM解碼器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | LQFP-128 |
| 文件頁(yè)數(shù)： | 26/116頁(yè) |
| 文件大小： | 787K |
| 代理商： | W88227QD |
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Preliminary/Confidential
Subject to change without notice
W88227F/W88227QD
- 22 -
1999/10/1 Rev: 0.70
2.2.3 Host Interface
The host interface is a standard ATAPI interface with enhanced Ultra DMA support. The Ultra DMA protocol
could double the current burst transfer rate of 16.6MB/sec to 66MB/sec without hardware changes such as
termination devices or different cabling.
2.2.3.1 Ultra DMA Mode Setting
This decoder is capable of supporting Ultra DMA Mode 4. Device firmware could claim that
Ultra DMA mode
4 and below are supported
in IDENTIFY DEVICE information.
The value of
UDT1-0 (8Ah,5-4)
defines the Ultra DMA Timing Factor,
udtf
, which control the timing of Ultra
DMA transfer.
Tcyc = ( 2 +
udtf
)
×
Tudma
where Tudma is clock period depends on setting of
UDTA (8Ah.6)
and
UCLKS (8Ah.3)
and Tcyc is Ultra DMA cycle time (from DSTROBE edge to DSTROBE edge)
Device firmware should set
udtf
according to the clock source and the assigned Ultra DMA transfer
mode after host issues SET FEATURE command. If there are frequent CRC errors in data-in bursts,
device firmware may switch system to slower Ultra DMA mode by increasing
udtf
to improve data
integrity.
Example
: If
UCLKS (8Ah.3)
is high and frequency of ACLK is 33.8688MHz, the
udtf
should be the following
value to abide by the determined Ultra DMA mode.
Ultra DMA
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
T2cyc Min. Spec.
230 ns
154 ns
115 ns
86 ns
57 ns
T2cyc
236 ns
177 ns
118 ns
88.6 ns
60 ns
udta
0
0
0
1
1
udtf
2
1
0
1
0
2.2.3.2 Ultra DMA Error Handling
Flag
UCRCOKb (30h.r3)
is used to determine if a CRC error event has occurred during latest Ultra DMA burst.
If
AUCRCEN (18h.2)
and
ASCEN (18h.5)
are both set high, the automatic status complete logic would not be
triggered if
UCRCOKb (30h.r3)
is high. Therefore, firmware should check
UCRCOKb (30h.r3)
flag after each
Ultra DMA burst. If a CRC error has occurred, firmware should set
CHK (37h.0)
to one and manually trigger
status complete.
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