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參數(shù)資料
| 型號(hào)： | W88227QD |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | ATAPI CD-ROM Decoder(支持ATAPI標(biāo)準(zhǔn)的CD-ROM解碼器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | LQFP-128 |
| 文件頁(yè)數(shù)： | 41/116頁(yè) |
| 文件大小： | 787K |
| 代理商： | W88227QD |
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Preliminary/Confidential
Subject to change without notice
W88227F/W88227QD
- 37 -
1999/10/1 Rev: 0.70
IR - Index Register
The Decoder Index Register is latched from uP Port-0 by the buillt-in 74373 at the falling edge of internal
ALE
signal. The high byte address of decoder register is defined by
CCSA0 (40h)
with default value 40h.
<example>: decoder register read (read VER)
MOV
DPTR,#0401Ah
MOVX A,@DPTR
<example>: decoder register write (set CCSA1 as 0xC0h)
MOV
A,#0C0h
MOV
DPTR,#04041h
MOVX @DPTR,A
PFAR - Packet FIFO Access Register - (read 00h)
While
SCoD (20h.2)
is high, the ATAPI Command Packet issued from host is received by the 12-byte Packet
FIFO. Flag
TENDb (01h.r6)
and
FPKT (30h.r1)
are used to check if the Packet FIFO is full. The
microprocessor can read the ATAPI Command Packet by repeatedly read register
PFAR (00h,r)
. Once the
FIFO becomes empty, the value FFh will be returned if microprocessor read PFAR.
The Packet FIFO can also be used to receive command parameter less than 12 bytes. First, the control bit
SCoD (20h.2)
is set high to select the Packet FIFO to be addressed by the ATAPI Data port. When
DRQ
(37h.3)
changes from 0 to 1, the lower 4 bits of
ATBLO (34h)
is latched as the FIFO threshold. Upon the
number of bytes in the FIFO reaches the threshold, flag
TENDb (01h.r6)
becomes active-low and flag
FPKT
(30h.r1)
becomes active-high. Once
FPKT
becomes high, any data writes to the ATAPI Data port is rejected.
INTCTL - Interrupt Control Register - (write 01h, read 11h)
Bit 7:
PFNEEN - Packet FIFO Not Empty Interrupt Enable
If this bit is high, decoder interrupt activates when
PFNEb (01h.r7)
becomes active-low. This bit is
clear to 0 after master reset, firmware reset.
Bit 6:
TENDEN - Transfer End Interrupt Enable
If this bit is high, decoder interrupt activates when
TENDb (01h.r6)
becomes active-low. This bit is
also automatically enabled if the host issues the PACKET Command (opcode A0h) while
HIIEN
(2Eh.w7)
is high and drive is selected. This bit is clear to 0 after master reset, firmware reset.
SRIEN - Sector Ready Interrupt Enable
Bit 5:
If this bit is high, decoder interrupt activates when
SRIb (01h.r5)
becomes active-low. This bit is clear
to 0 after master reset, firmware reset and decoder reset.
Bit 4:
reserved
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