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參數(shù)資料
| 型號： | W88227QD |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 消費家電 |
| 英文描述： | ATAPI CD-ROM Decoder(支持ATAPI標(biāo)準(zhǔn)的CD-ROM解碼器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | LQFP-128 |
| 文件頁數(shù)： | 80/116頁 |
| 文件大小： | 787K |
| 代理商： | W88227QD |
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Preliminary/Confidential
Subject to change without notice
W88227F/W88227QD
- 76 -
1999/10/1 Rev: 0.70
PSKCTL - Programmable System Clock Control Register - (read/write 59h)
This register should be set before the programmable system clock is enabled by setting
PSKEN (1Ah.w4)
high.
This register is 0 after master reset.
Bit 7:
PSKTEST (write only) - Programmable System Clock Test Enable
This bit is low after master reset and should be set low in normal operation. Setting this bit high is
only used for factory test.
Bit 7:
LOCKED (read) - Programmable System Clock Locked
This bit is high once the internal system clock is ever on lock with the programmed frequency.
Bit 6:
LOCKSEL (write) - Programmable System Clock Lock Select
If this bit is high, the internal system clock will keep the same delay path once the programmed
frequency is locked. This function keeps system clock at steady frequency, but the frequency may be
affected by temperature. If this bit is low, the internal system clock will be continuously adjusted to
fit the programmed frequency according to Crystal input and result in a various frequency.
Bit 6:
PSKEXE (read only) - Programmable System Clock Extreme Condition
This bit is low after master reset. The bit is high when the programmable system clock is at its lowest
or highest frequency. This indicates that the frequency equation, according to
PSK (59h.5-0),
may not
effective in this case.
Bit 5-0: PSK[5:0] - Programmable System Clock Factor
If
PSKEN (1Ah.w4)
and
PSKSEL (59h.w7)
are high, these six bits are used to controlled the
internal system frequency. The equation is:
frequency of system clock = frequency of XIN
×
(PSK[5:0] + 2)
÷
16
SCTC - Subcode Timer Control Register - (write 5Ah)
If
SBXCK (2Ch.w7)
and
CD2SC (2Ch.w5)
are both low, the clock used by subcode logic clock is controlled by
SUBCS2-0 (21h.w2-0)
unless any non-zero value is written into this register. The value of this register should
be calculated as follows:
( N + 2 )
×
tc
×
dsf = 11.3 / 2
where
tc
is the internal clock period(ex: 50nS for 20MHz crystal),
dsf
is the disk speed factor(ex: 4 for 4-fold speed drive).
There is no need to set this register if
SBCK (88h.w3)
is set high.
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