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參數資料
| 型號： | W88227QD |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 消費家電 |
| 英文描述： | ATAPI CD-ROM Decoder(支持ATAPI標準的CD-ROM解碼器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | LQFP-128 |
| 文件頁數： | 87/116頁 |
| 文件大小： | 787K |
| 代理商： | W88227QD |
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Preliminary/Confidential
Subject to change without notice
W88227F/W88227QD
- 83 -
1999/10/1 Rev: 0.70
DACTL - Digital Audio Control Register - (read/write 87h)
This register is 00h after chip reset and host reset.
Bit 7:
DAOEN - Digital Output Enable
If this bit is high, the digital audio data output through
pin DAOUT
.
Bit 6:
CTLSEL - Control Bit Source Select
If this bit is high, the 4 control bits of Q channel are defined by
QCTL3-0 (87h,3-0)
. Otherwise, these
4 control bits are extracted from external RAM. This bit is normal set low if the Q-channel extraction
work properly.
Bit 5-4: ACCU [1:0] - Clock Accuracy
These two bits are used as clock accuracy bits in digital audio output. These two bits are
usually set 00b.
Bit 3:0: QCTL [3:0] - Control Bits for Q Channel
If
CTLSEL (87h.6)
is high, these four bits are used as Q channel control bits in digital audio output.
FEACTL - Feature Control Register - (read/write 88h)
This register is 00h after chip reset and host reset.
Bit 7:
LECAS - Latch Data with External CAS Signal
If this bit is high, input DRAM data is latched by external CASH/L signal instead of rising edge of
internal clock. This function can eliminate the timing difference between DRAM data and its latch
signal caused by various internal chip delays, depending on circumstances. This bit should not be
used if
EDOEN (88h.1)
is high.
LREF - Long Refresh Cycle
Bit 6:
If this bit is high, the tRAS is 2.5 clocks instead 1.5 clocks for refresh cycle.
Bit 5: MRCD - Medium RAS to CAS Delay
The bit controls the timing of tRCD and tRP. If this bit is high the tRAS for RAS-only refresh is 2
clocks and CAS-Before-RAS is not affected (1.5 clocks).
Bit 4:
SDBS - Subcode and DSP Block Synchronization
This bit provides block synchronization of CD-DA format data. If this bit is high, the buffering of
incoming serial data and subcode to the external RAM will synchronize to the same block defined by
DDBH/L (29h/28h)
.
Bit 3: SBCK - Select BCK as subcode clock
When this bit is high, the
pin BCK
is selected as subcode reference clock instead of system clock.
This setting is suitable for drive using CAV subcode.
Bit 2: CAS8B - Eight CAS in One RAS Enable
When this bit is set low, maximum the number of Column Address Strobe is 8 instead of 4 in one
DRAM FPM cycle.
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