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參數資料
| 型號： | W88227QD |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 消費家電 |
| 英文描述： | ATAPI CD-ROM Decoder(支持ATAPI標準的CD-ROM解碼器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | LQFP-128 |
| 文件頁數： | 32/116頁 |
| 文件大小： | 787K |
| 代理商： | W88227QD |
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Preliminary/Confidential
Subject to change without notice
W88227F/W88227QD
- 28 -
1999/10/1 Rev: 0.70
2.2.4.10 Target Search
The target search logic is initialized by: (1) setting Search Limit, (2) setting Target and (3) setting
TARGEN
(80h.w7)
high. After the decoding is triggered through
CTRL0 (0Ah,w),
the first sector ready interrupt is
generated when: i) the target sector is found, ii) header is larger than target or iii) search limit is reached. If
event ii) or iii) occurs, the microprocessor may read out
HEAD0-2 (04h-06,r)
to determine the current distance
from target. Setting
LTTIEN (80h.w2)
and
TNFEN (80h.w1)
high can generate the associated interrupt flag on
SRIb (01h.r5)
before the target is found.
2.2.4.11 Automatic Header Comparison
The automatic header comparison logic is enabled by setting
TARGEN (80h.w7)
and
HCEEN (80h.w0)
high.
After the first target is found, the value in
TARGET (84h-86h)
increases from
(T - 1)
to
T
. And the decoder is
changed from disk-monitor mode to buffer-correction mode. Then
HEAD0-2 (04h-06h,r)
are compare with
TARGET (84h-86h)
and generate flag
HCEI (80h.r0)
at the end of EDC-checking. Unless flag
STAERR
(80h.r6)
or
HCEI (80h.r0)
is generated, the value in
TARGET (84h-86h)
is automatically incremented by one
and ready to be compared with next sector.
2.2.4.12 Status Collection
The status collection logic is enabled if any bit in the
Status-Mask-Register (8Ch-8Fh,w)
is set high. At the end
of EDC-checking, flag
STAERR (80h.r6)
becomes high if any status bit error that is enabled by its associating
mask bit occurs. The microprocessor can reduce the system overhead by checking
STAERR (80h.r6)
rather than
reading out
STAT (0Ch-0Fh,r)
.
2.2.4.13 Buffer-Independent-Correction
Buffer-Independent-Correction (BIC)
is enabled if
BICEN (9Ah.7)
is high. In
BIC
mode, the correction is
triggered when the sectors not decoded in buffer is larger than one. In
BIC
mode, the
DDBH/L (29h/28h)
controls the decoding block and increments at the end of EDC-checking, except erroneous sectors.
Meanwhile, the buffering block (internal) increments at each sync. Because of the independence of the
buffering block and decoding block, the
automatic repeat correction
can be enabled by setting
RCLIM3-0
(9Ch.3-0)
the maximum rounds of repeat correction.
2.2.4.14 Remove Frequent SRIb & Automatic Cache Management
Control bit
RMSRI (5Ch.0)
should be set when entering buffer mode and be disabled in decoder_off routine.
When
RMSRI (5Ch.0)
is high, flag
SRIb (01h.r5)
is generated only by
STAERR (80h.r6)
,
LASTBK (80h.r3)
or
HCEI (80h.r0)
.
So after the target is found and buffer-correction mode is enabled, the first interrupt is generated by
LASTBK
(80h.r3)
if there is no decoding error. Setting
RMSRI (5Ch.0)
high can reduce the overhead of microcontroller
while the automatic cache management is used.
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