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參數資料
型號: W89C840AF
廠商: WINBOND ELECTRONICS CORP
元件分類: 微控制器/微處理器
英文描述: 100/10Mbps Ethernet Controller
中文描述: 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP128
封裝: PLASTIC, QFP-128
文件頁數: 10/82頁
文件大小: 918K
代理商: W89C840AF
W89C840AF
-
10
-
Publication Release Date:October 2000
Revision 1.01
MMDIO
I/O
95
MII management data input/output.
This pin is used to transfer the MII control and status
information between PHY and MAC.
MCRS
I
98
Carrier Sense Signal:
This shall be asserted by PHY device when media is
busy, and deasserted when media is idle. MCRS shall
keep asserted, even at the duration of a collision.
MCOL
I
99
MII Collision detected:
This shall be asserted by the PHY device upon detecting
a collision happened over the medium. It will be asserted
and lasted until collision condition wholly vanishes.
MRXDV
I
100
MII Received data valid:
This pin is driven by PHY device. It will be asserted
when received data is coming and present, and
deasserted at the end of the frame. MRXDV is
synchronized with MRXCLK from PHY device.
MRXER
I
101
MII Received data error:
This pin is driven by PHY device. It indicates a data
conversion error is detected by PHY device. The
assertion of MRXER should be lasted for longer than a
period of MRXCLK. When MRXER asserted,
W89C840AF will report a Receive Error detection and a
CRC error
.
MRXCLK
I
102
MII Received clock source:
This clock is from PHY device. It will be either 25Mhz
or 2.5Mhz receive clock, determined by auto-negotiation
device in PHY and supported by W89C840AF. The
minimun duty cycle at its high state or low state of
MRXCLK should be 35% of the nominal period under
all condition. PHY device should drive MRXCLK as a
continuous clock.
MRXD[3:0]
I
107-104
Received data pins:
This is driven by external 100/10 Mbps PHY. MRXD
should be syncronized with clock source MRXCLK and
valid only when MRXDV is valid. MRXD[0] is the least
significant bit.
VDD
1,12,25,3
6,46,52,6
2,73,84,8
6,96,108,
119
Power supply pins.
GND
2,14,20,3
7,47,53,6
Ground pins.
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相關代理商/技術參數
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