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參數(shù)資料
| 型號： | W89C840AF |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 100/10Mbps Ethernet Controller |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數(shù)： | 59/82頁 |
| 文件大小： | 918K |
| 代理商： | W89C840AF |
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W89C840AF
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59
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Publication Release Date:October 2000
Revision 1.01
Typical MDIO/MDC Read Cycle
high impedance(z)
z
....
Idle
Start Read
PHYAD
REGAD
TA
Data
Idle
1 0
Z 0
MDC
MDIO
....
Preamble
0 1
Typical MDIO/MDC Write Cycle
z
....
Idle
Start Write
PHYAD
REGAD
TA
Data
Idle
1 0
MDC
MDIO
....
Preamble
0 1
0 1
Bit
Attribute
Bit name
Description
31:20
R
---
Reserved. Fixed at 0.
19
R
MDI
MII Management Port Data Input
The MII management input data drove, by the external PHY , on
the MIMDIO pin can be read from this bit when the MDSEL is
reset. The MDI reflects the logic level on the MIMDIO pin
instantly, no latching device is used for keeping the logic level
message.
18
R/W
MDSEL
MII Management Port Read/Write Select
The MIMDIO pin will be programmed as an input pin when the
MDSEL is reset. On the other hand, the MIMDIO will be an output
pin if MDSEL is set to high.
17
R/W
MDO
MII Management Port Write Data
The state of the MDO will be directly output through the MIMDIO
pin when the MIMDIO is performing an output pin. The serial
command of the external physical device should be written into
MDO serially with one bit data one MII management clock. The
accessed data sequence and timing are shown as the diagram
above .
16
R/W
MDC
MII Management Port Clock.
The state of the MDC will be directly driven on the MIMDC pin for
providing the MII management clock. To generate this clock
source, the MDC should be programmed as 1 and 0 with equal duty
cycle and timing width alternately. The AC timing specification
with respect to the MIMDC and MIMDIO should follow the media
independent interface(MII) specification defined in IEEE 802.3u.
15
R
---
Reserved. Fixed at 0.
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