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參數資料
| 型號： | W89C840AF |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 100/10Mbps Ethernet Controller |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數： | 51/82頁 |
| 文件大小： | 918K |
| 代理商： | W89C840AF |
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W89C840AF
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51
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Publication Release Date:October 2000
Revision 1.01
7
R/W
RBU
Receive Buffer Unavailable.
When there is no receive buffer available, this bit is set and the
receive process enters the suspend state.
When W89C840AF is first initialized, this bit will not be set even if
there is no buffer available. It will be set only when there has been
any available buffer and no available buffer afterwards.
The RBU will not accumulate the number of the receive buffer
unavailable event, i.e. the write an 1
RBU no matter how many times the receive buffer unavailable has
been occurred before the RBU is cleared.
value to RBU will clear the
6
R/W
RINI
Receive Interrupt
A high indicates that a frame has been received and the receive
status is transferred into the receive descriptors of the current frame.
5
R/W
IUF
Transmit FIFO Under-flow
A high indicates that the transmit FIFO had an under-flow error
during the packet transmission.
After the FIFO under-flow occurred, the transmit DMA will not
continue to fetch the un-transmitted data of the current frame but
fetch the descriptor of the current frame for looking for the last
descriptor of the current frame. The W89C840AF
state machine will write the transmit status to the last descriptor of
the current frame with a 1
value for the bit 1 of Transmit
Descriptor 0 (T00[1]).
transmit DMA
The W89C840AF will continue to transmit next packet when the
current frame transmit status is updated..
4
R/W
RERR
Receive Error.
A high indicates that the receive DMA detects a receive error
during the packet reception.
The receive DMA will set this bit when some prior received data of
the current incoming packet have been moved into the data buffer in
the host memory and some kind of error occurred when receiving
the posterior data of the current incoming packet from the MII bus.
The INTAB will be asserted when a receive error is detected and the
receive error interrupt enable is unmasked and the error packet will
be aborted.
3
R/W
REI
Receive Early Interrupt
The REI will be set when the number of the data of the incoming
frame, in long word unit, transferred to the data buffer reaches
Receive Early Interrupt Threshold specified by the register
C18/CNCR if Receive Early Interrupt On in the register
C18/CNCR is set.
This bit will be cleared automatically after Receive Interrupt (RINI)
or Receive Error (RERR) is set..
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相關代理商/技術參數 |
參數描述 |
|---|---|
| W89C840F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN NODE CONTROLLER |
| W89C841D | 制造商:WINBOND 制造商全稱:Winbond 功能描述:3-IN - 1 10/100M FAST ETHERNET CONTROLLER |
| W89C841F | 制造商:WINBOND 制造商全稱:Winbond 功能描述:3-IN - 1 10/100M FAST ETHERNET CONTROLLER |
| W89C841F/D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3-IN-1 100BASE-TX/FX & 10BASE-T Ethernet Controller |
| W89C880F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Hub Controller |
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