
W89C840AF
-
52
-
Publication Release Date:October 2000
Revision 1.01
2
R/W
TBU
Transmit Buffer Unavailable
A high indicates that there is no available transmit descriptor
during or after the packet transmission. The transmit process will
stay in suspend state.
The TBU will not accumulate the number of transmit buffer
unavailable event, i.e. write an 1 value to TBU will clear the TBU,
no matter how many times the transmit buffer unavailable has been
occurred before the TBU is cleared.
1
R/W
TIDLE
Transmit Process in Idle State.
A high indicates the transmit state machine is in the idle state.
0
R/W
TINI
Transmit Interrupt
The TINI will be set when a frame transmit is completed and the
FINT (bit 31) of Transmit Descriptor 1 (T01) is set.
C18/CNCR Network Configuration Register
The register C18/CNCR defines the configuration for the data transmission or receiving and the interrupt algorithm
for interrupt assertion.
Bit
Attribute
Bit name
Description
31
R/W
REIO
Receive Early Interrupt On
The receive early interrupt function will be enabled when the REIO
is set to high. Otherwise, the receive early interrupt function will be
disabled.
During receiving packet data, the W89C840AF will assert an
interrupt request when the bytes number of the received data, which
the receive DMA has moved them into the data buffer in the system
memory , excesses the receive early interrupt threshold.
30
R/W
TEIO
Transmit Early Interrupt On
The transmit early interrupt function will be enabled when the
TEIO is set to high. Otherwise, the transmit early interrupt function
will be disabled.
The W89C840AF will assert an early transmit interrupt when all
the current packet data have been moved into the 2 Kbytes transmit
FIFO no matter the data have been put onto the MII interface
completely or not.
29
R/W
FES
Fast Ethernet Select
W89C840AF run in 10 Mbps mode. To change this bit, the transmit
state machine must be in Idle state. The SQE test function will be
enabled when FES is reset to low.