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參數(shù)資料
| 型號： | W89C840AF |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 100/10Mbps Ethernet Controller |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數(shù)： | 14/82頁 |
| 文件大小： | 918K |
| 代理商： | W89C840AF |
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W89C840AF
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14
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Publication Release Date:October 2000
Revision 1.01
Receive direct memory access function
On receiving a data packet, the receive DMA function will
transfer these data from the internal receive FIFO
which has a size of 4k bytes to the host memory with the assistance of the on-chip PCI bus master. During the
transaction cycle, the media access controller(MAC) requests the receive DMA state machine to move the data in
the receive FIFO onto the PCI bus, and then move it to the host memory with a kind of data structure which is
constructed and described by descriptors.
A number of receive descriptors in the chip, which generated by chip itself, are used to specify the descriptor
structure and indicate the memory spaces for storing the received packet data. The receive descriptors are also used
to store the received packet status when a valid packet is received. Each descriptor has a size of 4 long words that
resides in the host memory.
The first 32 bits are used to keep the received packet status information. The second 32
bits are used to specify the descriptor structure type and the size of the received data buffer. The remains 64 bits are
used to specify the size and the address
of the allocated memory for this data buffer and the next one.
The received packet can be described by a single descriptor or multiple descriptors. It depends on the
configuration, previously set by software driver, and the received packet length. The received packet data also can be
stored in a single data buffer or multiple data buffers.
The descriptor structure can be either a ring structure or a chain structure. A mixed structure mode is also
allowed, too
.
In the descriptors with the ring structure, Host allocates a big continuous memory for keeping all the descriptor
information. Each descriptor can point to two data buffer addresses to store the received packet data. Though the
data buffers are not necessarily be contiguous, the descriptors must be contiguous one after the other.
The following figures describe the ring structures of receive descriptor.
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PDF描述 |
|---|---|
| W89C841F | 3-IN - 1 10/100M FAST ETHERNET CONTROLLER |
| W89C880F | 100Base-Tx/T4 Multiport Repeater Controller(100Base-Tx/T4多端口中繼器控制器) |
| W89C92 | PCMCIA ETHERNET NETWORK TWISTED PAIR INTERFACE CONTROLLER |
| W89C926 | PCMCIA ETHERNET NETWORK TWISTED PAIR INTERFACE CONTROLLER |
| W89C926F | 10M PCMCIA Ethernet Network Interface Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W89C840F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN NODE CONTROLLER |
| W89C841D | 制造商:WINBOND 制造商全稱:Winbond 功能描述:3-IN - 1 10/100M FAST ETHERNET CONTROLLER |
| W89C841F | 制造商:WINBOND 制造商全稱:Winbond 功能描述:3-IN - 1 10/100M FAST ETHERNET CONTROLLER |
| W89C841F/D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3-IN-1 100BASE-TX/FX & 10BASE-T Ethernet Controller |
| W89C880F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Hub Controller |
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