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參數資料
| 型號： | W89C840AF |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 100/10Mbps Ethernet Controller |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數： | 57/82頁 |
| 文件大小： | 918K |
| 代理商： | W89C840AF |
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W89C840AF
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57
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Publication Release Date:October 2000
Revision 1.01
4
R/W
RERRE
Receive Error Enable.
The Receive Error Interrupt will be enabled if both AIE(bit 15) and
RERRE are set to high, otherwise, the Receive Error Interrupt will
be disabled. The hardware interrupt will be asserted if all of the bit
AIE in C1C/CIMR, the bit RERRE in C1C/CIMR and the bit RERR
in C14/CISR are set to high.
3
R/W
REIE
Receive Early Interrupt Enable.
The Receive Early Interrupt will be enabled if both AIE(bit 15) and
REIE are set to high, otherwise, the Receive Early Interrupt will be
disabled. The hardware interrupt will be asserted if all of the bit
AIE in C1C/CIMR, the bit REIE in C1C/CIMR and the bit REI in
C14/CISR are set to high.
2
R/W
TBUE
Transmit Buffer Unavailable Enable.
The Transmit Buffer Unavailable Interrupt will be enabled if both
NIE(bit 16) and TBUE are set to high, otherwise, the Transmit
Buffer Unavailable Interrupt will be disabled. The hardware
interrupt will be asserted if all of the bitsNIE and TBUE in
C1C/CIMR and the bit TBU in C14/CISR are set to high.
1
R/W
TIE
Transmit Idle Enable.
The Transmit Idle Interrupt will be enabled if both AIE(bit 15) and
TIE are set to high, otherwise, the Transmit Idle Interrupt will be
disabled. The hardware interrupt will be asserted if all of the
C1C/CIMR AIE, C1C/CIMR TIE and C14/CISR TIDLE are set to
high.
0
R/W
TINTE
Transmit Interrupt Enable.
The Transmit Interrupt will be enabled if both NIE(bit 16) and
TINTE are set to high, otherwise, the Transmit Interrupt will be
disabled. The hardware interrupt will be asserted if all of the bits
NIE and TINTE in C1C/CIMR and the bit TINI in C14/CISR are
set to high.
C20/CFDCR Frame Discarded Counter Register
The register C20/CFDCR records the missed packet count and the FIFO overflow count.
Bit
Attribute
Bit name
Description
31
R
MRFO
More Receive FIFO Overflow
This bit is the overflow bit of the receive FIFO Overflow counter.
The actual number of the FIFO overflow must be more than the
number shown by the bits field RFOC if the MRFO is set to high.
This bit will be reset after a read operation
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相關代理商/技術參數 |
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| W89C841F/D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3-IN-1 100BASE-TX/FX & 10BASE-T Ethernet Controller |
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