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參數(shù)資料
型號(hào)： W89C840AF
廠商： WINBOND ELECTRONICS CORP
元件分類： 微控制器/微處理器
英文描述： 100/10Mbps Ethernet Controller
中文描述： 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP128
封裝： PLASTIC, QFP-128
文件頁(yè)數(shù)： 44/82頁(yè)
文件大?。?/td> 918K
代理商： W89C840AF
W89C840AF
-
44
-
Publication Release Date:October 2000
Revision 1.01
C1C
CIMR
00000000H
00000000H
C20
CFDCR
00000000H
00000000H
C24
CMIIR
00000000H
00000000H
C28
CBROA
00000000H
00000000H
C2C
CGTP
00000000H
00000000H
C30
CRDAR
00000000H
00000000H
C34
CRBAR
00000000H
00000000H
C38
CMA0
00000000H
not affected
C3C
CMA1
00000000H
not affected
C40
CPA0
00000000H
not affected
C44
CPA1
00000000H
not affected
C48
CBRCR
00000000H
not affected
C4c
CTDAR
00000000H
00000000H
C50
CTBAR
00000000H
00000000H
The detailed function and operation for each register in the W89C840AF will be described in the following
paragraph. There are total 21 registers to be described in register code order in this paragraph.
The full name of these registers are C00/CBCR Bus Control Register, C04/CTSDR Transmit Start Demand
Register,
C08/CRSDR Receive Start Demand Register, C0C/CRDLA Receive Descriptors List Addresses,
C10/CTDLA Transmit Descriptors List Addresses, C14/CISR Interrupt Status Register, C18/CNCR Network
Configuration Register, C1C/CIMR Interrupt Mask Register, C20/CFDCR Frame Discarded Counter Register,
C24/CMIIR MII Management and ROM Register, C28/CBROA Boot ROM Offset Address Register, C2C/CGTR
General Timer Register, C30/CRDAR Current Receive Descriptor Address Register, C34/CRBAR Current Receive
Buffer Address Register, C38/CMA0 Multicast Address Register 0, C3C/CMA1 Multicast Address Register 1,
C40/CPA0 Physical Address Register 0, C44/CPA1 Physical Address Register 1, C48/CBRCR Boot ROM Size
Configuration Register, C4C/CTDAR Current Transmit Descriptor Address Register and C50/CTBAR Current
Transmit Buffer Address Register.
C00/CBCR Bus Control Register:
This register defines the configuration of bus master, including the wait state control, the endian mode
control of the descriptor, cache alignment control, burst length control, descriptor skip length and the internal bus
access priority. In addition to the bus master control, the software reset will be performed after programming a
logic 1 to the software reset bit of C00/CBCR. Before writing data to the C00/CBCR, the transmit and receive
processes must be stopped. Otherwise the current transmit or receive operation will not be completed correctly.
The following table particularly describes the function of each bit of the register C00/CBCR.
Bit
Attribute
Bit name
Description
31:22
R
---
Reserved. Fixed at 0.
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W89C840F 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN NODE CONTROLLER
W89C841D 制造商:WINBOND 制造商全稱:Winbond 功能描述:3-IN - 1 10/100M FAST ETHERNET CONTROLLER
W89C841F 制造商:WINBOND 制造商全稱:Winbond 功能描述:3-IN - 1 10/100M FAST ETHERNET CONTROLLER
W89C841F/D 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3-IN-1 100BASE-TX/FX & 10BASE-T Ethernet Controller
W89C880F 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Hub Controller
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