
W89C840AF
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62
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Publication Release Date:October 2000
Revision 1.01
15:0
R/W
TIME
General Timer:
The bits field TIME shows the content of the general timer inside
the W89C840AF . The internal general timer will count down from
the pre-set value, a non zero value, programmed by the driver
program automatically once the write transaction to the register
C20/CGTR is completed. The time unit for the internal general
timer count down is approximately 2048 times the cycle duration of
the MII TXCLK. For instance, the count down time unit for a 25
Mhz MII TXCLK is approximately 82 us.
The C14/CISR bit 11 will be set when TIME of C2C/CGTR reach
zero. The TIME is default 0000H.
C30/CRDAR Current Receive Descriptor Address Register
The register C30/CRDAR shows that the start address of the receive descriptor which is used by the W89C840AF
receive DMA state machine to process the current receive frame.
Bit
Attribute
Bit name
Description
31:0
R
CRDA
Current Receive Descriptor Address.
The CRDA represents the start address of the current receive
descriptor which the W89C840AF
used to process the received frame.
receive DMA state machine is
C34/CRBAR Current Receive Buffer Address Register
The register C34/CRBAR shows that the start address of the host memory which will be used by the W89C840AF
receive DMA state machine to store the current aligned long word data of the current received frame.
Bit
Attribute
Bit name
Description
31:0
R
CRBA
Current Receive Buffer Address.
The CRBA contains the pointer current address in the on-using
buffer of the host memory which will be used by the W89C840AF
receive DMA state machine to store the current aligned long word
data of the current received frame.
C38/CMA0 Multicast Address Register 0
The C38/CMA0 defines the lower 32 bits of the total 64 bits multicast address hashing table.
Bit
Attribute
Bit name
Description
31:24
R/W
MAR3
Muticast Address 3.
The MAR3 defines the bit 24~31 of the hashing table.
23:16
R/W
MAR2
Muticast Address 2.
The MAR2 defines the bit 16~23 of the hashing table.