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參數資料
| 型號： | W89C840AF |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 100/10Mbps Ethernet Controller |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數： | 65/82頁 |
| 文件大小： | 918K |
| 代理商： | W89C840AF |
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W89C840AF
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65
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Publication Release Date:October 2000
Revision 1.01
C4C/CTDAR Current Transmit Descriptor Address Register
The C4C/CTDAR shows that the start address of the descriptor which the W89C840AF transmit DMA state
machine is used to process the current frame.
Bit
Attribute
Bit name
Description
31:0
R
CTDA
Current Transmit Descriptor Address.
The CTDA represents the start address of the current receive
descriptor which the W89C840AF
is used to process the transmit frame.
transmit DMA state machine
C50/CTBAR Current Transmit Buffer Address Register
The C50/CTBAR shows that the address of the system memory from which the W89C840AF
state machine will fetch the long word data and queue the data into the FIFO for transmission.
transmit DMA
Bit
Attribute
Bit name
Description
31:0
R
CTBA
Current Receive Buffer Address.
The CTBA contains the start address of the host memory from
which the W89C840AF transmit DMA state machine will fetch
the long word data and queue it into the FIFO for transmission.
Descriptors
As described at the beginning of the function description, descriptors are used to handle the control and status
information and the data of each received/transmitted frame. There are many information contained in
descriptors, W89C840AF totally implemented four registers for receiving descriptor and four registers for
transmiting descriptor respectively. They are one for status descriptor, one for control descriptor, and two for buffer
descriptors.
Receive Descriptors
R00, Receive Descriptor 0
The descriptor R00 is used to describe the received frame status.
After the current frame is received completely, the receive DMA state machine will update the valid status of the
current received frame into the first and the last descriptor of the current received frame.
The Receive Access Control(RAC) bit is valid on each descriptor of the current frame. The receive DMA state
machine will reset the RAC bit to release the descriptor for other receive operation when the data buffer pointed by
this descriptor is full.
Bit
Symbol
Description
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相關代理商/技術參數 |
參數描述 |
|---|---|
| W89C840F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN NODE CONTROLLER |
| W89C841D | 制造商:WINBOND 制造商全稱:Winbond 功能描述:3-IN - 1 10/100M FAST ETHERNET CONTROLLER |
| W89C841F | 制造商:WINBOND 制造商全稱:Winbond 功能描述:3-IN - 1 10/100M FAST ETHERNET CONTROLLER |
| W89C841F/D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3-IN-1 100BASE-TX/FX & 10BASE-T Ethernet Controller |
| W89C880F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Hub Controller |
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