
W89C840AF
-
42
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Publication Release Date:October 2000
Revision 1.01
15
R/W
PME_STS
PME Status.
This bit is set when the enabled Wake-Up Frame detector receives a
Wake-Up Frame or the enabled Magic Packet detector receives a
Magic Packet.
When PME_STS and PME_EN are set, the W89C840A asserts
PMEB.
Writing a 1 will clear PME_STS, RWUPF3, RWUPF2, RWUPF1,
RWUPF0, and RMGP.
Writing a 0 has no effect.
14:9
R
---
Fixed at 0.
8
R/W
PME_EN
PME Enable.
When PME_STS and PME_EN are set, the W89C840A asserts
PMEB.
This bit is reset when W89C840A changes from D3 (hot) to D0 (un-
initialized)
7:2
R
---
Reserved. Fixed at 0.
1:0
R/W
PW_STS
Power Management State.
00B --- W89C840A at D0 power management state
01B --- W89C840A at D1 power management state
11B --- W89C840A at D3 (hot) power state
Writing 10B has no effect.
The registers of W89C840AF
The W89C840AF is implemented many registers, listed in the table below, to perform the function
control and monitor the status of MAC. The general attributes of the W89C840AF register is described as the
following:
1) The W89C840AF registers are mapped into the host I/O or memory space.
2) The registers of the W89C840AF are long word-aligned. Each register consists of 32 bits and may be accessed
using any byte enable combinations with long word-aligned address.
3) The byte enabling and addressing must meet the specification for I/O access addressing rule when the register is
in I/O space.
4) Burst access to the W89C840AF register will be terminated after 1st data transfer completed with a Disconnect
without Data.
5) S/W reset will have the same effect as done by H/W reset on the W89C840AF register, except for the registers
or bits C00<0>, C38, C3c, C40, C44, C48.
6) Any read on the reserved register will be returned with 0
value.
The following table outlined all the control/status registers inside this chip and its offset address, and
summarized its function.