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參數(shù)資料
型號(hào): W89C840AF
廠商: WINBOND ELECTRONICS CORP
元件分類: 微控制器/微處理器
英文描述: 100/10Mbps Ethernet Controller
中文描述: 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP128
封裝: PLASTIC, QFP-128
文件頁數(shù): 18/82頁
文件大小: 918K
代理商: W89C840AF
W89C840AF
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18
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Publication Release Date:October 2000
Revision 1.01
data
buffer 1
data
buffer 2
data
buffer 3
data
buffer n
Rx
descriptor 1
Rx
descriptor 2
Rx
descriptor 3
Rx
descriptor n
4 Kbytes FIFO
data
from MAC
receive
DMA
state machine
controls
from MAC
status
control
data
status & control
PCI
master
PCI
PCI slave
As shown the above diagram, the receiving DMA state machine controls the data receiving processing and
the receiving status monitoring. On receiving the data packets, the receiving DMA will start to move these data
from FIFO to the data buffer, pointed by descriptors in the host memory if there is an available data buffer and the
byte count of the data received into the FIFO is larger than or equals to 64 bytes. If the received packet length is
less than 64 bytes and runt packet is not accepted, the receiving DMA will discard this invalid packet and give it a
record in the status register. The receiving DMA will start to move the data in FIFO after the full packet is
received if runt packet is accepted. Once a valid packet is received, the receive DMA will advance the descriptor
pointer for the next incoming packet. However, the current data buffer and the descriptor will be re-used if the
current receiving packet is not a valid packet, i.e. the receive state machine will ignore the previously received
packet data in the data buffer. Each received packet will be treated as a valid packet if it meets the requirement in
the bits 3, 4, 5, 6 and 7 of C18/CNCR register. In some case of the data buffer unavailable temporarily, the
incoming packet data from media will be queued in the FIFO temporarily, meanwhile, the receive DMA will enter
suspend state at this time and a buffer unavailable interrupt will be issued. The receive DMA will start moving the
data whenever the data buffer is available and a receiving operation is demanded, On the other hand, the data will
be lost if the FIFO is overflowed. The receiving status, e.g., the receive descriptor access status, the receive
completion status, the received data byte count, the received packet error status, the received packet data type, ...
and so on., will be written back into the descriptor by the receive DMA when the packet is received successfully.
During receiving a packet, the receive DMA will release the access right of the descriptor and the data
buffer to the driver immediately after the free byte space of the data buffers pointed by the current descriptor is
counted down to zero and the receive DMA will fetch the next available descriptor for the current incoming packet.
It is known that the LLC layer data is packed into the first 64 bytes of the packet in most application program. The
driver and the upper layer application program can read the protocol messages carried in the first 64 bytes of the
incoming packet when the receive DMA release the descriptor and the data buffer for the current incoming packet,
although the current incoming packet is not yet received completely. The function of the receive DMA releasing
the descriptor and the data buffer which have been used during receiving a packet allows the software and the
hardware to
process the receiving packet concurrently. This parallel processing of software and the hardware can
improve the system receiving performance significantly.
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