
W89C840AF
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7
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Publication Release Date:October 2000
Revision 1.01
IRDYB
IO/STS
17
Initiator Ready:
The IRDYB is asserted by the current initiator to
indicate the ability to complete the data transfer at the
current data phase. The initiator asserts IRDYB to
indicate the valid write data, or to indicate it is ready to
accept the read data.
More than or exactly one wait state
will be inserted if IRDYB is deasserted during the
current transaction. Data is transferred at the clock
rising edge
when both IRDYB and TRDYB are asserted
at the same time.
TRDYB
IO/STS
18
Target Ready:
Asserted by the current target to indicate ability to
complete data transfer at the current data phase. When
W89C840AF is operating at the bus slave mode
,
it
asserts TRDYB to indicate that the valid read data
presents on the bus or to indicate it is ready to accept
data. Wait states will be inserted if TRDYB is
deasserted. Data is transferred at the rising edge of the
PCI clock when IRDYB and TRDYB are both asserted
at the same time.
STOPB
IO/STS
20
PCI Stop:
Asserted by the current target to request PCI bus master
to stop the current transaction.
IDSEL
I
4
PCI Initialization Device Select:
Asserted by host to signal the configuration access
request to W89C840AF.
DEVSELB
IO/STS
19
PCI Device Select:
Asserted by the current target to indicate that it has
finished decoding its address as the current access
target. When W89C840AF is the current master, it
checks if the target asserted this signal within 5 PCI
clocks after having issued command. If not,
W89C840AF will abort the access operation, releases
PCI bus access right and acts no more bus master. When
W89C840AF is the target, it asserts DEVSELB in a
medium speed, i.e., within 2 clocks.
REQB
O/TS
117
PCI Request:
Asserted by W89C840AF to request bus ownership.
REQB will be tri-stated when RSTB asserted.
GNTB
I/TS
116
PCI Grant:
Asserted by host to grant that W89C840AF have got the
bus ownership. When RSTB asserted, W89C840AF will
ignore GNTB.