
W89C840AF
-
19
-
Publication Release Date:October 2000
Revision 1.01
When the incoming packet is received completely, the receive DMA will write the same copy of the packet
receiving status to the first descriptor and the last descriptor of the current frame respectively. The receiving status
includes the receive completion status, the received byte count, the receive error type,...etc. All of the status is
specified in the receive descriptor R00. When the software and hardware are concurrently processing , the software
needs not to go back to read the first descriptor of the current incoming packet for knowing the receive completed
status or other receiving status when it is processing the last descriptor and the data buffer of the current incoming
packet. But, if there is only one descriptor needed for the current incoming packet, all of receiving status will be
updated in the unique descriptor.
The W89C840AF transmit DMA function performs the data transfer from the host memory through on-
chip PCI bus master into the internal 2 Kbytes transmit FIFO. The transmit DMA state machine will request the
MAC to send out the data in the FIFO onto the MII.
The transmit descriptor is used to set the transmit configuration and to point to the transmit data buffer
locations. Each packet to be transmitted can be described by one or more than one descriptor. And each descriptor
consists of four consecutive long word. The first long word(T00) is for the transmit frame status register. The T00
describes the descriptor access right control, the packet transmitting status,...etc. The second long word(T01) is for
the control register used to specify the transmission configuration, including the CRC inhibit control, padding
function control, the descriptor structure control ... etc. The third long word (T02) is for the first data buffer pointer
and the fourth long word is used as the second data buffer pointer
in the ring structure.
The transmit descriptor list also can be constructed as a ring structure or a chain structure. The mixed chain
and ring structure is also allowed to be constructed. The scheme for constructing the transmit descriptor list is
same as the one for receiving descriptor list, but, each transmit data buffer size is limited to under 1 Kbytes other
than the 2 Kbytes receiving data buffer. In the consequence of the 1 Kbytes transmit data buffer, each descriptor
can point to a maximum two 1 Kbytes data buffer totally.
The data flow of the packet transmission is shown as the following diagram