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參數資料
| 型號： | W89C840AF |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 100/10Mbps Ethernet Controller |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數： | 55/82頁 |
| 文件大小： | 918K |
| 代理商： | W89C840AF |
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W89C840AF
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55
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Publication Release Date:October 2000
Revision 1.01
5
R/W
ABP
Accept Broadcast Packet.
When set, all incoming packets with a broadcast address will be
accepted. When reset, the incoming packets with a broadcast
address will be rejected. Default 1.
4
R/W
AMP
Accept Multicast Packet.
When set, all incoming packets with a multicast address match the
node multicast address table (MAR7 ~ MAR0) will be accepted.
When reset, all incoming packets with a multicast address
(excluding broadcast address) will be rejected. Default 1.
3
R/W
APP
Accept All Physical Packet.
When set, all incoming packets with unicast address will be
accepted. When reset, only the incoming packets with destination
address matching the physical address of the node will be accepted.
Default 0.
2
R
---
Reserved. Fixed at 0.
1
R/W
RXON
Receive On.
When set, the receive process will be started (leave the Idle state, at
first, and fetch the receive descriptor according to the configuration
of the register C0C/CRDLA ).
When reset, the receive state machine will be stopped after the
current frame is completed.
The C0C/CRDLA, C40/PAR0, C44/PAR1, C38/MAR0 and
C3C/MAR1 registers must be programmed before setting the
RXON high.
0
R
---
Reserved. Fixed at 0.
C1C/CIMR Interrupt Mask Register
The register C1C/CIMR controls the interrupt enable corresponding to the bits in the register C14/CISR.
Bit
Attribute
Bit name
Description
31:17
R
---
Reserved. Fixed at 0.
16
R/W
NIE
Normal Interrupt Enable.
The Normal Interrupt will be enabled if the NIE is set to high.
The Normal Interrupt is disabled when the NIE is reset to low. The
hardware interrupt will be asserted if both the NIE bit of the
C1C/CIMR and the NIR bit of the C14/CISR NIR are set to high.
15
R/W
AIE
Abnormal Interrupt Enable.
The Abnormal Interrupt will be enabled if the AIE is set to high.
The Abnormal Interrupt is disabled when the AIE is reset to low.
The hardware interrupt will be asserted if both the AIE bit of the
C1C/CIMR and the AIR bit of the C14/CISR AIR are set to high.
14
R
---
Reserved. Fixed at 0.
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相關代理商/技術參數 |
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