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參數資料
| 型號： | W90221F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | PA-RISC Embedded Micro-Controller(惠普PA-RISC結構的32位嵌入式微控制器) |
| 中文描述： | PA - RISC的嵌入式微控制器（惠普的PA - RISC結構的32位嵌入式微控制器） |
| 文件頁數： | 10/174頁 |
| 文件大?。?/td> | 2102K |
| 代理商： | W90221F |
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The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.
10
Versi on 0. 4, March/2000
FRAME#
I/O
74
PCI Cycle Frame is driven by the current master to indicate
the beginning and duration of an access. FRAME# is
asserted to indicate a bus transaction is beginning. While
FRAME# is asserted, data transfers continue. When FRAM#
is deasserted, the transaction is in the final data phase or has
completed.
PCI Initiator Ready indicates the bus master
complete the current data phase of the transaction. A data
phase is completed on any clock both IRDY# and TRDY# are
sampled asserted. During a write, IRDY# indicates that valid
data is present on PDA[31:0]. During a read, it indicates the
master is prepared to accept data. Wait cycles are inserted
until both IRDY# and TRDY# are asserted together.
PCI Parity is even parity across PDA[31:0] and C/BE[3:0]#.
PPAR is stable and valid one clock after the address phase.
For data phases, PPAR is stable and valid one clock after
either IRDY# is asserted on a write transaction or TRDY# is
asserted on a read transaction. (PPAR has the same timing
as PDA[31:0], but it is delayed by one clock.) The mater
drives PPAR for address and write data phases; the target
drives PPAR for read data phase.
During
normal mode
, this bus
inputs
8-bit digital
components of YCbCr 4:2:2 video-in data from external
video controller (ex. TV decoder or MPEG decoder).
During
test mode
, this bus
outputs
8-bit digital components
of YCbCr 4:2:2 video-out generated by internal video
accelerator (VA).
Horizontal Sync of video-in frames. The content of VAconf[]
determines the polarity of this signal.
Vertical Sync of video-in frames. The content of VAconf[]
determines the polarity of this signal.
This clock source serves as VMI bus pixel clock (27MHz). A
precise
27MHz
clock source shall be connected to this pin.
During
composite
video mode (NTSC, PAL), this pin is
analog "composite video" output.
During
S-Video
mode, this pin is analog "
chrominance
"
output.
During
monitor
mode, this analog output supplies current
corresponding to the "
blue
" intensity of the pixel being
displayed.
(To maintain IBM VGA compatibility, R-G-B outputs are
typically terminated to monitor's ground with a 75 omv 2%
resistor. This resistor, in parallel with the 75 omv resistor in
the monitor, will yield a 37.5 omv impedance to ground. For
a full-scale voltage of 700 mV, full-scale current output will
be
18.7mA
.)
IRDY#
I/O
72
ability to
PPAR
I/O
76
8-bit Video-In (VMI) Bus :
VIN[0:7]
I/O
114~121
HSI
I
113
VSI
I
112
VCLK
I
110
Display and DAC interface :
CP2/C/Blue
AO
128
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