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參數資料
型號： W90221F
廠商： WINBOND ELECTRONICS CORP
英文描述： PA-RISC Embedded Micro-Controller(惠普PA-RISC結構的32位嵌入式微控制器)
中文描述： PA - RISC的嵌入式微控制器（惠普的PA - RISC結構的32位嵌入式微控制器）
文件頁數： 40/174頁
文件大小： 2102K
代理商： W90221F
=
The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.
40
Versi on 0. 4, March/2000
- The frame sync (SYNC) is asserted immediately as the first bit of transmit and receive
data.
- The frame sync (SYNC) is asserted for one "serial word length" which determined by
CFGH[8:11].
Serial word length = CFGH[8:11] + 1
- The frame sync rate (sampling rate) and SCLK frequence follow eq (5.1.6b) and (5.1.6a)
respectively on master mode and determined by external devices on slave mode.
- The transmit FIFO and receive FIFO is configued as 48x16 if "serial word length" <= 16,
and will be configured as 24x32 if "serial word length" > 16.
- The shifting data bits on SDI and SDO are always MSB first.
- If serial word length is not 16 or 32, it is software responsibility to left(MSB) justify the
transmit
data words before writing it to transmit FIFO, the received data before being written into
receive
FIFO is righ(LSB) justified automatically by SSI module where the unfilled MSBs are
catneted
with logic 0s.
- SSI module always shifts out logic 0s on each frame sync if transmit FIFO is empty at that
time.
- A receiver FIFO interrupt will be asserted (when RX-FIFO interrupt is enable) if the
received
data words exceeds the receive FIFO's threshold level. Likewise, a transmitter FIFO
interrupt
will be asserted (when TX-FIFO interrupt is enable) if the available data words in transmit
FIFO
is lower than its threshold level.
- Fig 6.1.5-2 shows a standard long framing transfer where serial word length is 3
(CFGH[8:11] =
2), words per frame is 3 (CFGH[12:15]=2) and bits per frame is 9 (CFGL[0:7] = 10).
SCLK
(5.1.6c)
SYNC
SDI
D1_1
D1_2
D1_3
D2_1
D2_2
D2_3
D3_1
D3_2
D3_3
D1_1
D1_2
SDO
D1_1
D1_2
D1_3
D2_1
D2_2
D2_3
D3_1
D3_2
D3_3
D1_1
D1_2
Fig 5.1.6-2 SSI long framing transfer
- Short Framing : When CFGH[3] is set to logic 0, SSI is operated in long framing mode. The following
features
are included in short framing mode
consists of the following features.
- The frame sync (SYNC) is asserted for one SCLK immediately before the first bit of
transmit
and receive data.
- The frame sync (SYNC) is asserted for one SCLK period.
- All other features are the same as long framing mode.
- Fig 6.1.5-3 shows a standard short framing transfer where serial word length is 3
(CFGH[8:11] =
2), words per frame is 3 (CFGH[12:15]=2) and bits per frame is 9 (CFGL[0:7] = 10).
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