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參數(shù)資料
| 型號(hào)： | W90221F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | PA-RISC Embedded Micro-Controller(惠普PA-RISC結(jié)構(gòu)的32位嵌入式微控制器) |
| 中文描述： | PA - RISC的嵌入式微控制器（惠普的PA - RISC結(jié)構(gòu)的32位嵌入式微控制器） |
| 文件頁(yè)數(shù)： | 8/174頁(yè) |
| 文件大小： | 2102K |
| 代理商： | W90221F |
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The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.
8
Versi on 0. 4, March/2000
GPIO[12]
I/O
151
If parallel port is enable (port 0x3e[4] = 1x), this pin serve as
ECP "
nFault
" (input).
If parallel port is not enable (port 0x3e[4:5] = 00), this pin
provides general purpose I/O functionality (inout).
During "clock test" mode (port 0x3e[4] = 01), this pin outputs
internal
MCLK_data
(output).
These two pins always provide general purpose I/O
functionality.
If parallel port is enable (port 0x3e[4] = 1x), this pin serve as
ECP "
nAutoFd
".
If parallel port is not enable (port 0x3e[4:5] = 0x), this pin
outputs PCI bridge Grant two "GNT2#".
If parallel port is enable (port 0x3e[4] = 1x), this pin serve as
ECP "
nStrobe
".
If parallel port is not enable (port 0x3e[4:5] = 0x), this pin
outputs PCI bridge Grant three "GNT3#".
If parallel port is enable (port 0x3e[4] = 1x), this pin serve as
ECP "
nAck
".
If parallel port is not enable (port 0x3e[4:5] = 0x), this pin
inputs Master request two "PREQ2#".
If parallel port is enable (port 0x3e[4] = 1x), this pin serve as
ECP "
Busy
".
If parallel port is not enable (port 0x3e[4:5] = 0x), this pin
inputs Master request three "PREQ3#".
for more detail description of the PCI signals please refer to the
PCI LOCAL
BUS SPECIFICATION
During
PCI
cycles : If AIO is enable, this signal shall not
connect to any PCI bus master
During
AIO
cycles : Asserted low indicating a AIO command
cycle is ongoing
During
PCI
cycles : These pins serve as highest byte of PCI
32-bit address/data bus.
During
AIO memory
cycles0 : These pins serve as highest
byte of 24-bit address lines (XA[8:31])
During
AIO IO
cycles. : These serve as high byte of 16-bit
data lines (XD[15:0]).
During
PCI
cycles : These pins serve as bits 16-31 of PCI
32-bit address/data bus.
During
AIO
cycles : These pins serve as lower 16-bit of 24-
bit address lines (XA[8:31]).
During
PCI
cycles : These pins serve as lowest byte of PCI
32-bit address/data bus.
During
AIO memory
cycles : These pins serve as the 8-bit
data lines.
During
AIO IO
cycles : These pins serve as low byte of 16-bit
data lines (XD[15:0]).
During
PCI
cycles : Bit-3 of command/byte bus
During
AIO
cycles : AIO chip-select for its IO devices
During
PCI
cycles : Bit-2 of command/byte bus
During
AIO
cycles : AIO chip-select for its memory devices
GPIO[13:14]
I/O
137, 138
GNT2#/
nAutoFd
O
153
GNT3#/
nStrobe
O
154
PREQ2#/
nAck
I
155
PREQ3#/
Busy
I
156
PCI/AIO Bus Bridge :
INTD#/
XGLBCS#
O
32
PDA[31:24]/
XA[8:15]/
XD[15:8]
I/O
100-98, 94,
93, 90-88
PDA[23:8]/
XA[16:31]
I/O
85, 84, 83,
82, 80-77, 63-
61, 59-57, 50,
49
45-38
PDA[7:0]/
XD[15:8]
I/O
COMBE[3]/
AIOCS#
COMBE[2]/
XROMCS#
I/O
87
I/O
76
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