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參數資料
型號: W90221F
廠商: WINBOND ELECTRONICS CORP
英文描述: PA-RISC Embedded Micro-Controller(惠普PA-RISC結構的32位嵌入式微控制器)
中文描述: PA - RISC的嵌入式微控制器(惠普的PA - RISC結構的32位嵌入式微控制器)
文件頁數: 11/174頁
文件大小: 2102K
代理商: W90221F
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The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.
11
Versi on 0. 4, March/2000
CP1/Y/Green
AO
129
During
composite
video mode (NTSC, PAL), this pin is
analog "composite video" output.
During
S-Video
mode, this pin is analog "
luminance
" output.
During
monitor
mode, this analog output supplies current
corresponding to the "
green
" intensity of the pixel being
displayed.
During
composite
video mode (NTSC, PAL), this pin is
analog "composite video" output.
During
S-Video
mode, this pin left no connection.
During
monitor
mode, this analog output supplies current
corresponding to the "
red
" intensity of the pixel being
displayed.
Horizontal Sync of the displayed graphic output. The content
of VAconf[] determines the polarity of this signal.
Vertical Sync of the displayed graphic output. The content of
VAconf[] determines the polarity of this signal.
Voltage Reference Out; Bypass and decouple the voltage
reference with 0.1uF ceramic capacitor to the TVDD.
The decoupling capacitor shall be as close to the chip as
possible. This pin as well as "COMP" are used to control the
current of internal current sources are exactly equal to "Iref".
Voltage Reference Out; Bypass and decouple the voltage
reference with 0.1uF ceramic capacitor to the TVDD.
The decoupling capacitor shall be as close to the chip as
possible. This pin as well as "COMP" are used to control the
current of internal current sources are exactly equal to "Iref".
Compensation pin. It shall be decoupled with a 0.1uF
ceramic capacitor to TVDD. The decoupling capacitor shall
be as close to the chip as possible.
Current Source Adjusting Resistor. This pin is used to adjust
the full scale current of TV's analog outputs. A resistor
shall be connected between this pin and TVSS. (The DAC's
"Iref" of current mirrors are adjusted by this pin). The
Iref
is
approximate to
1.16V/RSET
.
External Vref input. This signal supplies the DAC's
"bandgap" output from a external 1.235V voltage source. A
0.1uF bpass capacitor should be always connected between
this pin and TVDD. ("bandgap" is an voltage stabilizer of
voltage-reference-generator "Vref"). This pin may left
unconnected.
During
EDO mode
, these signals are served as RAS0#,
RAS1# that used to latch the row address MA[0:11] lines
into the DRAM. Each signal is used to select one DRAM
bank.
During
SDRAM mode
, these signals are served as CS0L#,
CS1L# that indicates the command decoder is enable or
disable.
CP0/Red
AO
130
HSO
O
134
VSO
O
132
VREF
AO
125
VREF
AO
125
COMP
AO
127
RSET
AO
126
EXTVREF
AI
123
Memory Controller Interface :
CS0L#/RAS0#,
CS1L#/RAS1#
O
195, 197
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