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參數資料
型號： W90221F
廠商： WINBOND ELECTRONICS CORP
英文描述： PA-RISC Embedded Micro-Controller(惠普PA-RISC結構的32位嵌入式微控制器)
中文描述： PA - RISC的嵌入式微控制器（惠普的PA - RISC結構的32位嵌入式微控制器）
文件頁數： 15/174頁
文件大小： 2102K
代理商： W90221F
=
The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.
15
Versi on 0. 4, March/2000
Single
27MHz
oscillator to generate all clock sources
- PLL input clock (13.5MHz)
- CPU clock range : 80, 90, 100, 110, 120, 130, 150, 180MHz
- Video-Accelerator clock (27MHz, 13.5MHz)
- system clock (CPU-clock/2, /3, /4)
- SDRAM clock (CPU-clock/1, /1.5, /2)
- UART, Timer clock (13.5MHz)
Optional SCLK input for SSI interface as SSI operation in slave mode
Power-on setting :
- MD[
31
] pull high to enable internal PLL unit
MD[
28-30
] used to choose CPUCLK from 80MHz to 180MHz,
MD[
26-27
] set 2'b00 to choose 1/3 CPUCLK,
2'b01 to choose 1/4 CPUCLK,
2'b10 to choose 1/5 CPUCLK
2'b10 to choose 1/6 CPUCLK as EXTCLK
MD[
25
] pull high to set X_SCLK (of SSI unit) to output mode (SCLK master mode)
MD[
24
] set high to choose OSC clock as GFXCLK/2
MD[
20-23
]
are reserved for further extension
- CTM[0-3] (0xf00001d8) memorize states of
MD[20~23]
during power-on interval (refer
to pp.66)
(Firmware reads these bits to know what kind of target board is
operating.)
- DRAMctrl2[2-3] (0xf000003e) defines MCLK frequencies (refer to pp.28)
- TVTWH[12-15] (0xf0000178) defines the format of video output (refer to pp.52)
- VPTC[17] (0xf000017c) defines the direction of 8-bit video-in bus (refer to pp.53)
Related Pins :
- DPCLK (input) :
This clock source serves as internal PLL input as well as VA's system clock. A precise 27MHz clock
source
shall be connected to this pin during normal operation.
- VCLK (input) :
This clock source serves as VMI bus pixel clock (27MHz). A precise 27MHz clock source shall be
connected to
this pin.
- GFXCLK (input) :
This clock source serves as pixel clock, 36MHz to 50MHz, using in 800x600 non-interlace monitor. For
TV
system, this clock may pull high or low externally. Meanwhile, GFXCLK may also serves as system
OSC (for baud
rate or timer adjustment), if MD[24] is pull high externally.
- SCLK (in/out) :
This pin is the serial bit clock between SSI and codec devices. The SCLK may be input or output
depending
on SSI operated in slave- or master-mode respectively.
.
- VDDL, VSSL :
Dedicate power/ground pins for internal PLL unit. VDDL shall connects a 3.3V voltage source.
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