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參數資料
型號： W90221F
廠商： WINBOND ELECTRONICS CORP
英文描述： PA-RISC Embedded Micro-Controller(惠普PA-RISC結構的32位嵌入式微控制器)
中文描述： PA - RISC的嵌入式微控制器（惠普的PA - RISC結構的32位嵌入式微控制器）
文件頁數： 39/174頁
文件大小： 2102K
代理商： W90221F
=
The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond.
39
Versi on 0. 4, March/2000
Features :
supports "long framing" and "short framing" (synchronous, frame-based protocol)
provides "master mode" and "slave mode"
build-in two 48x16 (or 24x32) data fifo to accelerate transmit/receive operation
Programmable data bits per one frame (sampling rate) : 1 ~ 256 bits/frame
Programmable data bits per word (resolution of each sampling) : 1 ~ 32 bits/word
Programmable multi-word (per frame) transfer : 1 ~ 16 words/frame
Related Pins :
- SDI (input) : This pin contains the input data shifted from external audio/telephony codec devices
- SDO (output)
: This pin contains the output data shifted to external audio/telephony codec
devices
- SYNC (in/out) : This pin is the frame synchronization signal between SSI and codec devices. The SYNC
may be
input or output depending on SSI operated in slave- or master-mode respectively.
- SCLK
(in/out)
: This pin is the serial bit clock between SSI and codec devices. Likewise,
The SCLK may be
input or output depending on SSI operated in slave- or master-mode
respectively.
Operation Modes :
- Master Mode : Once CFGH[2] is set to logic 1 and MD[25] is pull high, SSI is operated in master mode,
and the
SYNC (determines the sampling rate) and SCLK is drived by SSI module to external codec
devices.
SCLK frequence = EXTCLK/[2*(CFGL[8:15] + 1)]
SYNC period
=
SCLK * (CFGL[0:7] + 1)
- Slave Mode : Once CFGH[2] is set to logic 0 and MD[25] is pull down, SSI is operated in slave mode,
the SCLK
and SYNC are drived externally (may be from codec devices). So the sampling rate
and SCLK fre-
quence are determined by external devices, however software driver still need to properly
set "serial
data bit length" (CFGH[8:10] ) as well as "data words per frame" ( CFGH[12:15] ) to make
SSI
module working correctly.
- Loop mode : This mode (CFGH[1] =1) aims at selftesting. When this bit is set, serial data-out "SDO" is
connected
to serial data-in "SDI" internally and SDO pin fixed at logic 0 state. Besides, if
Loop
and
Master
mode are chose concurrently, SSI module will not issue SYNC until TX-FIFO contains at
least one
data word.
- Long Framing : When CFGH[3] is set to logic 1, SSI is operated in long framing mode. The following
features are
included in long framing mode :
consists of the following features.
- The SSI module always samples receive date (SDI) on the falling edge of SCLK, whereas
always
pushes transmit data (SDO) on the rising edge of SCLK.
(5.1.6a)
(5.1.6b)
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